Lines Matching full:assigned
210 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
212 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
213 assigned-clock-rates = <0>, <100000000>;
237 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
239 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
240 assigned-clock-rates = <0>, <100000000>;
381 assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>,
384 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
385 assigned-clock-rates = <0>, <884736000>, <12288000>;
417 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
420 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
421 assigned-clock-rates = <0>, <884736000>, <36864000>;
428 assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>,
431 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
432 assigned-clock-rates = <0>, <884736000>, <36864000>;
443 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
444 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
451 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
452 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
496 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
497 assigned-clock-rates = <400000000>;