Lines Matching +full:imx27 +full:- +full:uart
1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/clock/imx6sx-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include "imx6sx-pinfunc.h"
12 #address-cells = <1>;
13 #size-cells = <1>;
16 * pre-existing /chosen node to be available to insert the
57 #address-cells = <1>;
58 #size-cells = <0>;
61 compatible = "arm,cortex-a9";
64 next-level-cache = <&L2>;
65 operating-points = <
72 fsl,soc-operating-points = <
79 clock-latency = <61036>; /* two CLK32 periods */
80 #cooling-cells = <2>;
86 clock-names = "arm", "pll2_pfd2_396m", "step",
88 arm-supply = <®_arm>;
89 soc-supply = <®_soc>;
90 nvmem-cells = <&cpu_speed_grade>;
91 nvmem-cell-names = "speed_grade";
95 ckil: clock-ckil {
96 compatible = "fixed-clock";
97 #clock-cells = <0>;
98 clock-frequency = <32768>;
99 clock-output-names = "ckil";
102 osc: clock-osc {
103 compatible = "fixed-clock";
104 #clock-cells = <0>;
105 clock-frequency = <24000000>;
106 clock-output-names = "osc";
109 ipp_di0: clock-ipp-di0 {
110 compatible = "fixed-clock";
111 #clock-cells = <0>;
112 clock-frequency = <0>;
113 clock-output-names = "ipp_di0";
116 ipp_di1: clock-ipp-di1 {
117 compatible = "fixed-clock";
118 #clock-cells = <0>;
119 clock-frequency = <0>;
120 clock-output-names = "ipp_di1";
123 anaclk1: clock-anaclk1 {
124 compatible = "fixed-clock";
125 #clock-cells = <0>;
126 clock-frequency = <0>;
127 clock-output-names = "anaclk1";
130 anaclk2: clock-anaclk2 {
131 compatible = "fixed-clock";
132 #clock-cells = <0>;
133 clock-frequency = <0>;
134 clock-output-names = "anaclk2";
138 compatible = "fsl,imx6sx-mqs";
144 compatible = "arm,cortex-a9-pmu";
145 interrupt-parent = <&gpc>;
150 compatible = "usb-nop-xceiv";
151 #phy-cells = <0>;
155 #address-cells = <1>;
156 #size-cells = <1>;
157 compatible = "simple-bus";
158 interrupt-parent = <&gpc>;
162 compatible = "mmio-sram";
165 #address-cells = <1>;
166 #size-cells = <1>;
171 compatible = "mmio-sram";
174 #address-cells = <1>;
175 #size-cells = <1>;
179 intc: interrupt-controller@a01000 {
180 compatible = "arm,cortex-a9-gic";
181 #interrupt-cells = <3>;
182 interrupt-controller;
185 interrupt-parent = <&intc>;
188 L2: cache-controller@a02000 {
189 compatible = "arm,pl310-cache";
192 cache-unified;
193 cache-level = <2>;
194 arm,tag-latency = <4 2 3>;
195 arm,data-latency = <4 2 3>;
205 clock-names = "bus", "core", "shader";
206 power-domains = <&pd_pu>;
209 dma_apbh: dma-apbh@1804000 {
210 compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
216 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
217 #dma-cells = <1>;
218 dma-channels = <4>;
222 gpmi: nand-controller@1806000{
223 compatible = "fsl,imx6sx-gpmi-nand";
224 #address-cells = <1>;
225 #size-cells = <1>;
227 reg-names = "gpmi-nand", "bch";
229 interrupt-names = "bch";
235 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
238 dma-names = "rx-tx";
243 compatible = "fsl,aips-bus", "simple-bus";
244 #address-cells = <1>;
245 #size-cells = <1>;
249 spba-bus@2000000 {
250 compatible = "fsl,spba-bus", "simple-bus";
251 #address-cells = <1>;
252 #size-cells = <1>;
257 compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
262 dma-names = "rx", "tx";
270 clock-names = "core", "rxtx0",
279 #address-cells = <1>;
280 #size-cells = <0>;
281 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
286 clock-names = "ipg", "per";
291 #address-cells = <1>;
292 #size-cells = <0>;
293 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
298 clock-names = "ipg", "per";
303 #address-cells = <1>;
304 #size-cells = <0>;
305 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
310 clock-names = "ipg", "per";
315 #address-cells = <1>;
316 #size-cells = <0>;
317 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
322 clock-names = "ipg", "per";
327 compatible = "fsl,imx6sx-uart",
328 "fsl,imx6q-uart", "fsl,imx21-uart";
333 clock-names = "ipg", "per";
335 dma-names = "rx", "tx";
340 compatible = "fsl,imx6sx-esai", "fsl,imx35-esai";
348 clock-names = "core", "mem", "extal",
352 dma-names = "rx", "tx";
357 #sound-dai-cells = <0>;
358 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
363 clock-names = "ipg", "baud";
365 dma-names = "rx", "tx";
366 fsl,fifo-depth = <15>;
371 #sound-dai-cells = <0>;
372 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
377 clock-names = "ipg", "baud";
379 dma-names = "rx", "tx";
380 fsl,fifo-depth = <15>;
385 #sound-dai-cells = <0>;
386 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
391 clock-names = "ipg", "baud";
393 dma-names = "rx", "tx";
394 fsl,fifo-depth = <15>;
399 compatible = "fsl,imx6sx-asrc", "fsl,imx53-asrc";
409 clock-names = "mem", "ipg", "asrck_0",
417 dma-names = "rxa", "rxb", "rxc",
419 fsl,asrc-rate = <48000>;
420 fsl,asrc-width = <16>;
426 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
431 clock-names = "ipg", "per";
432 #pwm-cells = <3>;
436 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
441 clock-names = "ipg", "per";
442 #pwm-cells = <3>;
446 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
451 clock-names = "ipg", "per";
452 #pwm-cells = <3>;
456 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
461 clock-names = "ipg", "per";
462 #pwm-cells = <3>;
466 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
471 clock-names = "ipg", "per";
472 fsl,stop-mode = <&gpr 0x10 1 0x10 17>;
477 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
482 clock-names = "ipg", "per";
483 fsl,stop-mode = <&gpr 0x10 2 0x10 18>;
488 compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt";
493 clock-names = "ipg", "per";
497 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
501 gpio-controller;
502 #gpio-cells = <2>;
503 interrupt-controller;
504 #interrupt-cells = <2>;
505 gpio-ranges = <&iomuxc 0 5 26>;
509 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
513 gpio-controller;
514 #gpio-cells = <2>;
515 interrupt-controller;
516 #interrupt-cells = <2>;
517 gpio-ranges = <&iomuxc 0 31 20>;
521 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
525 gpio-controller;
526 #gpio-cells = <2>;
527 interrupt-controller;
528 #interrupt-cells = <2>;
529 gpio-ranges = <&iomuxc 0 51 29>;
533 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
537 gpio-controller;
538 #gpio-cells = <2>;
539 interrupt-controller;
540 #interrupt-cells = <2>;
541 gpio-ranges = <&iomuxc 0 80 32>;
545 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
549 gpio-controller;
550 #gpio-cells = <2>;
551 interrupt-controller;
552 #interrupt-cells = <2>;
553 gpio-ranges = <&iomuxc 0 112 24>;
557 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
561 gpio-controller;
562 #gpio-cells = <2>;
563 interrupt-controller;
564 #interrupt-cells = <2>;
565 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
569 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
573 gpio-controller;
574 #gpio-cells = <2>;
575 interrupt-controller;
576 #interrupt-cells = <2>;
577 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
581 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
589 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
596 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
603 clks: clock-controller@20c4000 {
604 compatible = "fsl,imx6sx-ccm";
608 #clock-cells = <1>;
610 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2";
614 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
615 "syscon", "simple-mfd";
621 reg_vdd1p1: regulator-1p1 {
622 compatible = "fsl,anatop-regulator";
623 regulator-name = "vdd1p1";
624 regulator-min-microvolt = <1000000>;
625 regulator-max-microvolt = <1200000>;
626 regulator-always-on;
627 anatop-reg-offset = <0x110>;
628 anatop-vol-bit-shift = <8>;
629 anatop-vol-bit-width = <5>;
630 anatop-min-bit-val = <4>;
631 anatop-min-voltage = <800000>;
632 anatop-max-voltage = <1375000>;
633 anatop-enable-bit = <0>;
636 reg_vdd3p0: regulator-3p0 {
637 compatible = "fsl,anatop-regulator";
638 regulator-name = "vdd3p0";
639 regulator-min-microvolt = <2800000>;
640 regulator-max-microvolt = <3150000>;
641 regulator-always-on;
642 anatop-reg-offset = <0x120>;
643 anatop-vol-bit-shift = <8>;
644 anatop-vol-bit-width = <5>;
645 anatop-min-bit-val = <0>;
646 anatop-min-voltage = <2625000>;
647 anatop-max-voltage = <3400000>;
648 anatop-enable-bit = <0>;
651 reg_vdd2p5: regulator-2p5 {
652 compatible = "fsl,anatop-regulator";
653 regulator-name = "vdd2p5";
654 regulator-min-microvolt = <2250000>;
655 regulator-max-microvolt = <2750000>;
656 regulator-always-on;
657 anatop-reg-offset = <0x130>;
658 anatop-vol-bit-shift = <8>;
659 anatop-vol-bit-width = <5>;
660 anatop-min-bit-val = <0>;
661 anatop-min-voltage = <2100000>;
662 anatop-max-voltage = <2875000>;
663 anatop-enable-bit = <0>;
666 reg_arm: regulator-vddcore {
667 compatible = "fsl,anatop-regulator";
668 regulator-name = "vddarm";
669 regulator-min-microvolt = <725000>;
670 regulator-max-microvolt = <1450000>;
671 regulator-always-on;
672 anatop-reg-offset = <0x140>;
673 anatop-vol-bit-shift = <0>;
674 anatop-vol-bit-width = <5>;
675 anatop-delay-reg-offset = <0x170>;
676 anatop-delay-bit-shift = <24>;
677 anatop-delay-bit-width = <2>;
678 anatop-min-bit-val = <1>;
679 anatop-min-voltage = <725000>;
680 anatop-max-voltage = <1450000>;
683 reg_pcie: regulator-vddpcie {
684 compatible = "fsl,anatop-regulator";
685 regulator-name = "vddpcie";
686 regulator-min-microvolt = <725000>;
687 regulator-max-microvolt = <1450000>;
688 anatop-reg-offset = <0x140>;
689 anatop-vol-bit-shift = <9>;
690 anatop-vol-bit-width = <5>;
691 anatop-delay-reg-offset = <0x170>;
692 anatop-delay-bit-shift = <26>;
693 anatop-delay-bit-width = <2>;
694 anatop-min-bit-val = <1>;
695 anatop-min-voltage = <725000>;
696 anatop-max-voltage = <1450000>;
699 reg_soc: regulator-vddsoc {
700 compatible = "fsl,anatop-regulator";
701 regulator-name = "vddsoc";
702 regulator-min-microvolt = <725000>;
703 regulator-max-microvolt = <1450000>;
704 regulator-always-on;
705 anatop-reg-offset = <0x140>;
706 anatop-vol-bit-shift = <18>;
707 anatop-vol-bit-width = <5>;
708 anatop-delay-reg-offset = <0x170>;
709 anatop-delay-bit-shift = <28>;
710 anatop-delay-bit-width = <2>;
711 anatop-min-bit-val = <1>;
712 anatop-min-voltage = <725000>;
713 anatop-max-voltage = <1450000>;
717 compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
718 interrupt-parent = <&gpc>;
721 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
722 nvmem-cell-names = "calib", "temp_grade";
728 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
736 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
744 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
747 snvs_rtc: snvs-rtc-lp {
748 compatible = "fsl,sec-v4.0-mon-rtc-lp";
754 snvs_poweroff: snvs-poweroff {
755 compatible = "syscon-poweroff";
763 snvs_pwrkey: snvs-powerkey {
764 compatible = "fsl,sec-v4.0-pwrkey";
768 wakeup-source;
783 src: reset-controller@20d8000 {
784 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
788 #reset-cells = <1>;
792 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
794 interrupt-controller;
795 #interrupt-cells = <3>;
797 interrupt-parent = <&intc>;
799 clock-names = "ipg";
802 #address-cells = <1>;
803 #size-cells = <0>;
805 power-domain@0 {
807 #power-domain-cells = <0>;
810 pd_pu: power-domain@1 {
812 #power-domain-cells = <0>;
813 power-supply = <®_soc>;
817 pd_disp: power-domain@2 {
819 #power-domain-cells = <0>;
829 pd_pci: power-domain@3 {
831 #power-domain-cells = <0>;
832 power-supply = <®_pcie>;
838 compatible = "fsl,imx6sx-iomuxc";
842 gpr: iomuxc-gpr@20e4000 {
843 compatible = "fsl,imx6sx-iomuxc-gpr",
844 "fsl,imx6q-iomuxc-gpr", "syscon";
849 compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
854 clock-names = "ipg", "ahb";
855 #dma-cells = <3>;
857 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
862 compatible = "fsl,aips-bus", "simple-bus";
863 #address-cells = <1>;
864 #size-cells = <1>;
869 compatible = "fsl,sec-v4.0";
870 #address-cells = <1>;
871 #size-cells = <1>;
874 interrupt-parent = <&intc>;
879 clock-names = "mem", "aclk", "ipg", "emi_slow";
882 compatible = "fsl,sec-v4.0-job-ring";
888 compatible = "fsl,sec-v4.0-job-ring";
895 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
902 ahb-burst-config = <0x0>;
903 tx-burst-size-dword = <0x10>;
904 rx-burst-size-dword = <0x10>;
909 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
915 ahb-burst-config = <0x0>;
916 tx-burst-size-dword = <0x10>;
917 rx-burst-size-dword = <0x10>;
922 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
931 ahb-burst-config = <0x0>;
932 tx-burst-size-dword = <0x10>;
933 rx-burst-size-dword = <0x10>;
938 #index-cells = <1>;
939 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
945 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
947 interrupt-names = "int0", "pps";
955 clock-names = "ipg", "ahb", "ptp",
957 fsl,num-tx-queues = <3>;
958 fsl,num-rx-queues = <3>;
959 fsl,stop-mode = <&gpr 0x10 3>;
973 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
979 clock-names = "ipg", "ahb", "per";
980 bus-width = <4>;
985 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
991 clock-names = "ipg", "ahb", "per";
992 bus-width = <4>;
997 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
1003 clock-names = "ipg", "ahb", "per";
1004 bus-width = <4>;
1009 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
1015 clock-names = "ipg", "ahb", "per";
1016 bus-width = <4>;
1021 #address-cells = <1>;
1022 #size-cells = <0>;
1023 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1031 #address-cells = <1>;
1032 #size-cells = <0>;
1033 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1041 #address-cells = <1>;
1042 #size-cells = <0>;
1043 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1050 memory-controller@21b0000 {
1051 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
1057 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
1059 interrupt-names = "int0", "pps";
1067 clock-names = "ipg", "ahb", "ptp",
1069 fsl,stop-mode = <&gpr 0x10 4>;
1074 #address-cells = <2>;
1075 #size-cells = <1>;
1076 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
1080 fsl,weim-cs-gpr = <&gpr>;
1085 #address-cells = <1>;
1086 #size-cells = <1>;
1087 compatible = "fsl,imx6sx-ocotp", "syscon";
1091 cpu_speed_grade: speed-grade@10 {
1099 tempmon_temp_grade: temp-grade@20 {
1105 compatible = "fsl,imx6sx-sai";
1111 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1112 dma-names = "rx", "tx";
1118 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
1124 compatible = "fsl,imx6sx-sai";
1130 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1131 dma-names = "rx", "tx";
1137 #address-cells = <1>;
1138 #size-cells = <0>;
1139 compatible = "fsl,imx6sx-qspi";
1141 reg-names = "QuadSPI", "QuadSPI-memory";
1145 clock-names = "qspi_en", "qspi";
1150 #address-cells = <1>;
1151 #size-cells = <0>;
1152 compatible = "fsl,imx6sx-qspi";
1154 reg-names = "QuadSPI", "QuadSPI-memory";
1158 clock-names = "qspi_en", "qspi";
1163 compatible = "fsl,imx6sx-uart",
1164 "fsl,imx6q-uart", "fsl,imx21-uart";
1169 clock-names = "ipg", "per";
1171 dma-names = "rx", "tx";
1176 compatible = "fsl,imx6sx-uart",
1177 "fsl,imx6q-uart", "fsl,imx21-uart";
1182 clock-names = "ipg", "per";
1184 dma-names = "rx", "tx";
1189 compatible = "fsl,imx6sx-uart",
1190 "fsl,imx6q-uart", "fsl,imx21-uart";
1195 clock-names = "ipg", "per";
1197 dma-names = "rx", "tx";
1202 compatible = "fsl,imx6sx-uart",
1203 "fsl,imx6q-uart", "fsl,imx21-uart";
1208 clock-names = "ipg", "per";
1210 dma-names = "rx", "tx";
1215 #address-cells = <1>;
1216 #size-cells = <0>;
1217 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1226 compatible = "fsl,aips-bus", "simple-bus";
1227 #address-cells = <1>;
1228 #size-cells = <1>;
1232 spba-bus@2240000 {
1233 compatible = "fsl,spba-bus", "simple-bus";
1234 #address-cells = <1>;
1235 #size-cells = <1>;
1245 clock-names = "disp-axi", "csi_mclk", "dcic";
1250 compatible = "fsl,imx6sx-pxp", "fsl,imx6ull-pxp";
1254 clock-names = "axi";
1255 power-domains = <&pd_disp>;
1265 clock-names = "disp-axi", "csi_mclk", "dcic";
1270 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1276 clock-names = "pix", "axi", "disp_axi";
1277 power-domains = <&pd_disp>;
1282 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1288 clock-names = "pix", "axi", "disp_axi";
1289 power-domains = <&pd_disp>;
1295 reg-names = "vadc-vafe", "vadc-vdec";
1298 clock-names = "vadc", "csi";
1299 power-domains = <&pd_disp>;
1305 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1309 clock-names = "adc";
1310 fsl,adck-max-frequency = <30000000>, <40000000>,
1316 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1320 clock-names = "adc";
1321 fsl,adck-max-frequency = <30000000>, <40000000>,
1327 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1335 #address-cells = <1>;
1336 #size-cells = <0>;
1337 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1342 clock-names = "ipg", "per";
1347 compatible = "fsl,imx6sx-uart",
1348 "fsl,imx6q-uart", "fsl,imx21-uart";
1353 clock-names = "ipg", "per";
1355 dma-names = "rx", "tx";
1360 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1365 clock-names = "ipg", "per";
1366 #pwm-cells = <3>;
1370 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1375 clock-names = "ipg", "per";
1376 #pwm-cells = <3>;
1380 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1385 clock-names = "ipg", "per";
1386 #pwm-cells = <3>;
1390 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1395 clock-names = "ipg", "per";
1396 #pwm-cells = <3>;
1401 compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
1403 reg-names = "dbi", "config";
1404 #address-cells = <3>;
1405 #size-cells = <2>;
1407 bus-range = <0x00 0xff>;
1409 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
1410 num-lanes = <1>;
1412 interrupt-names = "msi";
1413 #interrupt-cells = <1>;
1414 interrupt-map-mask = <0 0 0 0x7>;
1415 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1423 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
1424 power-domains = <&pd_disp>, <&pd_pci>;
1425 power-domain-names = "pcie", "pcie_phy";