Lines Matching +full:0 +full:x02004000
58 #size-cells = <0>;
60 cpu0: cpu@0 {
63 reg = <0>;
97 #clock-cells = <0>;
104 #clock-cells = <0>;
111 #clock-cells = <0>;
112 clock-frequency = <0>;
118 #clock-cells = <0>;
119 clock-frequency = <0>;
125 #clock-cells = <0>;
126 clock-frequency = <0>;
132 #clock-cells = <0>;
133 clock-frequency = <0>;
151 #phy-cells = <0>;
163 reg = <0x008f8000 0x4000>;
164 ranges = <0 0x008f8000 0x4000>;
172 reg = <0x00900000 0x20000>;
173 ranges = <0 0x00900000 0x20000>;
183 reg = <0x00a01000 0x1000>,
184 <0x00a00100 0x100>;
190 reg = <0x00a02000 0x1000>;
200 reg = <0x01800000 0x4000>;
211 reg = <0x01804000 0x2000>;
226 reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
237 dmas = <&dma_apbh 0>;
246 reg = <0x02000000 0x100000>;
253 reg = <0x02000000 0x40000>;
258 reg = <0x02004000 0x4000>;
260 dmas = <&sdma 14 18 0>,
261 <&sdma 15 18 0>;
266 <&clks 0>, <&clks 0>, <&clks 0>,
268 <&clks 0>, <&clks 0>,
280 #size-cells = <0>;
282 reg = <0x02008000 0x4000>;
292 #size-cells = <0>;
294 reg = <0x0200c000 0x4000>;
304 #size-cells = <0>;
306 reg = <0x02010000 0x4000>;
316 #size-cells = <0>;
318 reg = <0x02014000 0x4000>;
329 reg = <0x02020000 0x4000>;
334 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
341 reg = <0x02024000 0x4000>;
350 dmas = <&sdma 23 21 0>,
351 <&sdma 24 21 0>;
357 #sound-dai-cells = <0>;
359 reg = <0x02028000 0x4000>;
364 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
371 #sound-dai-cells = <0>;
373 reg = <0x0202c000 0x4000>;
378 dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
385 #sound-dai-cells = <0>;
387 reg = <0x02030000 0x4000>;
392 dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
400 reg = <0x02034000 0x4000>;
403 <&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>,
404 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
405 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
406 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
407 <&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>,
427 reg = <0x02080000 0x4000>;
437 reg = <0x02084000 0x4000>;
447 reg = <0x02088000 0x4000>;
457 reg = <0x0208c000 0x4000>;
467 reg = <0x02090000 0x4000>;
472 fsl,stop-mode = <&gpr 0x10 1 0x10 17>;
478 reg = <0x02094000 0x4000>;
483 fsl,stop-mode = <&gpr 0x10 2 0x10 18>;
489 reg = <0x02098000 0x4000>;
498 reg = <0x0209c000 0x4000>;
505 gpio-ranges = <&iomuxc 0 5 26>;
510 reg = <0x020a0000 0x4000>;
517 gpio-ranges = <&iomuxc 0 31 20>;
522 reg = <0x020a4000 0x4000>;
529 gpio-ranges = <&iomuxc 0 51 29>;
534 reg = <0x020a8000 0x4000>;
541 gpio-ranges = <&iomuxc 0 80 32>;
546 reg = <0x020ac000 0x4000>;
553 gpio-ranges = <&iomuxc 0 112 24>;
558 reg = <0x020b0000 0x4000>;
565 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
570 reg = <0x020b4000 0x4000>;
577 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
582 reg = <0x020b8000 0x4000>;
590 reg = <0x020bc000 0x4000>;
597 reg = <0x020c0000 0x4000>;
605 reg = <0x020c4000 0x4000>;
616 reg = <0x020c8000 0x1000>;
627 anatop-reg-offset = <0x110>;
633 anatop-enable-bit = <0>;
642 anatop-reg-offset = <0x120>;
645 anatop-min-bit-val = <0>;
648 anatop-enable-bit = <0>;
657 anatop-reg-offset = <0x130>;
660 anatop-min-bit-val = <0>;
663 anatop-enable-bit = <0>;
672 anatop-reg-offset = <0x140>;
673 anatop-vol-bit-shift = <0>;
675 anatop-delay-reg-offset = <0x170>;
688 anatop-reg-offset = <0x140>;
691 anatop-delay-reg-offset = <0x170>;
705 anatop-reg-offset = <0x140>;
708 anatop-delay-reg-offset = <0x170>;
729 reg = <0x020c9000 0x1000>;
737 reg = <0x020ca000 0x1000>;
744 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
745 reg = <0x020cc000 0x4000>;
748 compatible = "fsl,sec-v4.0-mon-rtc-lp";
750 offset = <0x34>;
757 offset = <0x38>;
758 value = <0x60>;
759 mask = <0x60>;
764 compatible = "fsl,sec-v4.0-pwrkey";
774 reg = <0x020d0000 0x4000>;
779 reg = <0x020d4000 0x4000>;
785 reg = <0x020d8000 0x4000>;
793 reg = <0x020dc000 0x4000>;
803 #size-cells = <0>;
805 power-domain@0 {
806 reg = <0>;
807 #power-domain-cells = <0>;
812 #power-domain-cells = <0>;
819 #power-domain-cells = <0>;
831 #power-domain-cells = <0>;
839 reg = <0x020e0000 0x4000>;
845 reg = <0x020e4000 0x4000>;
850 reg = <0x020ec000 0x4000>;
865 reg = <0x02100000 0x100000>;
869 compatible = "fsl,sec-v4.0";
872 reg = <0x2100000 0x10000>;
873 ranges = <0 0x2100000 0x10000>;
882 compatible = "fsl,sec-v4.0-job-ring";
883 reg = <0x1000 0x1000>;
888 compatible = "fsl,sec-v4.0-job-ring";
889 reg = <0x2000 0x1000>;
896 reg = <0x02184000 0x200>;
900 fsl,usbmisc = <&usbmisc 0>;
902 ahb-burst-config = <0x0>;
903 tx-burst-size-dword = <0x10>;
904 rx-burst-size-dword = <0x10>;
910 reg = <0x02184200 0x200>;
915 ahb-burst-config = <0x0>;
916 tx-burst-size-dword = <0x10>;
917 rx-burst-size-dword = <0x10>;
923 reg = <0x02184400 0x200>;
931 ahb-burst-config = <0x0>;
932 tx-burst-size-dword = <0x10>;
933 rx-burst-size-dword = <0x10>;
940 reg = <0x02184800 0x200>;
946 reg = <0x02188000 0x4000>;
959 fsl,stop-mode = <&gpr 0x10 3>;
964 reg = <0x0218c000 0x4000>;
974 reg = <0x02190000 0x4000>;
986 reg = <0x02194000 0x4000>;
998 reg = <0x02198000 0x4000>;
1010 reg = <0x0219c000 0x4000>;
1022 #size-cells = <0>;
1024 reg = <0x021a0000 0x4000>;
1032 #size-cells = <0>;
1034 reg = <0x021a4000 0x4000>;
1042 #size-cells = <0>;
1044 reg = <0x021a8000 0x4000>;
1052 reg = <0x021b0000 0x4000>;
1058 reg = <0x021b4000 0x4000>;
1069 fsl,stop-mode = <&gpr 0x10 4>;
1077 reg = <0x021b8000 0x4000>;
1088 reg = <0x021bc000 0x4000>;
1092 reg = <0x10 4>;
1096 reg = <0x38 4>;
1100 reg = <0x20 4>;
1106 reg = <0x021d4000 0x4000>;
1110 <&clks 0>, <&clks 0>;
1113 dmas = <&sdma 31 24 0>, <&sdma 32 24 0>;
1119 reg = <0x021d8000 0x4000>;
1125 reg = <0x021dc000 0x4000>;
1129 <&clks 0>, <&clks 0>;
1132 dmas = <&sdma 33 24 0>, <&sdma 34 24 0>;
1138 #size-cells = <0>;
1140 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1151 #size-cells = <0>;
1153 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1165 reg = <0x021e8000 0x4000>;
1170 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1178 reg = <0x021ec000 0x4000>;
1183 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1191 reg = <0x021f0000 0x4000>;
1196 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1204 reg = <0x021f4000 0x4000>;
1209 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1216 #size-cells = <0>;
1218 reg = <0x021f8000 0x4000>;
1229 reg = <0x02200000 0x100000>;
1236 reg = <0x02240000 0x40000>;
1240 reg = <0x02214000 0x4000>;
1251 reg = <0x02218000 0x4000>;
1260 reg = <0x0221c000 0x4000>;
1271 reg = <0x02220000 0x4000>;
1283 reg = <0x02224000 0x4000>;
1294 reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1306 reg = <0x02280000 0x4000>;
1317 reg = <0x02284000 0x4000>;
1328 reg = <0x02288000 0x4000>;
1336 #size-cells = <0>;
1338 reg = <0x0228c000 0x4000>;
1349 reg = <0x022a0000 0x4000>;
1354 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1361 reg = <0x022a4000 0x4000>;
1371 reg = <0x022a8000 0x4000>;
1381 reg = <0x022ac000 0x4000>;
1391 reg = <0x0022b0000 0x4000>;
1402 reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>;
1407 bus-range = <0x00 0xff>;
1408 ranges = <0x81000000 0 0 0x08f80000 0 0x00010000 /* downstream I/O */
1409 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
1414 interrupt-map-mask = <0 0 0 0x7>;
1415 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1416 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1417 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1418 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;