Lines Matching +full:0 +full:x10b0
15 reg = <0x80000000 0x80000000>;
21 pinctrl-0 = <&pinctrl_led>;
33 pinctrl-0 = <&pinctrl_vcc_sd3>;
118 assigned-clock-rates = <0>, <0>, <24576000>;
123 pinctrl-0 = <&pinctrl_esai>;
127 assigned-clock-rates = <0>, <24576000>;
133 pinctrl-0 = <&pinctrl_enet1>;
141 #size-cells = <0>;
143 ethphy0: ethernet-phy@0 {
145 reg = <0>;
157 pinctrl-0 = <&pinctrl_enet2>;
166 pinctrl-0 = <&pinctrl_flexcan1>;
173 pinctrl-0 = <&pinctrl_flexcan2>;
180 pinctrl-0 = <&pinctrl_uart1>;
186 pinctrl-0 = <&pinctrl_usdhc3>;
200 pinctrl-0 = <&pinctrl_usdhc4>;
212 MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22 0x10b0
218 MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
219 MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
220 MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9
221 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
222 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
223 MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
224 MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
225 MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
226 MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
227 MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
228 MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
229 MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
230 MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
231 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
237 MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9
238 MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
239 MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1
240 MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1
241 MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1
242 MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1
243 MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
244 MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
245 MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
246 MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
247 MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
248 MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
254 MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030
255 MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030
256 MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030
257 MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030
258 MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030
259 MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030
260 MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030
261 MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030
262 MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030
263 MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030
269 MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020
270 MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020
276 MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020
277 MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020
283 MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
284 MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1
290 MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
291 MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
297 MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24 0x17059
303 MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0
309 MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1
310 MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1
316 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
317 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
318 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
319 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
320 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
321 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
322 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
323 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
324 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
325 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
326 MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
327 MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
333 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
334 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
335 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
336 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
337 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
338 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
339 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
340 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
341 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
342 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
348 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
349 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
350 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
351 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
352 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
353 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
354 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
355 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
356 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
357 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
363 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
364 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
365 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
366 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
367 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
368 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
369 MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
370 MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
376 MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
382 MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0
390 pinctrl-0 = <&pinctrl_i2c2>;
395 reg = <0x48>;
396 clocks = <&anaclk2 0>;
406 reg = <0x04>;
408 pinctrl-0 = <&pinctrl_egalax_int>;
416 reg = <0x08>;
518 reg = <0x68>;
527 pinctrl-0 = <&pinctrl_i2c3>;
532 reg = <0x30>;
539 reg = <0x32>;
547 pinctrl-0 = <&pinctrl_spdif>;
555 pinctrl-0 = <&pinctrl_wdog>;