boot/dts/dra76x.dtsi

1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
12 		target-module@42c01900 {
13 			compatible = "ti,sysc-dra7-mcan", "ti,sysc";
15 			#address-cells = <1>;
16 			#size-cells = <1>;
20 			reg-names = "rev", "sysc", "syss";
21 			ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET |
23 			ti,syss-mask = <1>;
25 			clock-names = "fck";
30 				reg-names = "m_can", "message_ram";
31 				interrupt-parent = <&gic>;
34 				interrupt-names = "int0", "int1";
36 				clock-names = "hclk", "cclk";
37 				bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
45 	target-module@1b0000 {			/* 0x489b0000, ap 25 34.0 */
46 		compatible = "ti,sysc-omap4", "ti,sysc";
49 		reg-names = "rev", "sysc";
50 		ti,sysc-midle = <SYSC_IDLE_FORCE>,
52 		ti,sysc-sidle = <SYSC_IDLE_FORCE>,
55 		clock-names = "fck";
56 		#address-cells = <1>;
57 		#size-cells = <1>;
61 			compatible = "ti,dra76-cal";
65 			reg-names = "cal_top",
69 			ti,camerrx-control = <&scm_conf 0x6dc>;
72 				#address-cells = <1>;
73 				#size-cells = <0>;
86 /* MCAN interrupts are hard-wired to irqs 67, 68 */
88 	ti,irqs-skip = <10 67 68 133 139 140>;
93 		#clock-cells = <0>;
94 		compatible = "ti,divider-clock";
96 		ti,max-div = <63>;
98 		ti,bit-shift=<20>;
99 		ti,latch-bit=<26>;
100 		assigned-clocks = <&dpll_gmac_h14x2_ctrl_ck>;
101 		assigned-clock-rates = <80000000>;
105 		#clock-cells = <0>;
106 		compatible = "ti,mux-clock";
109 		ti,bit-shift = <29>;
110 		ti,latch-bit=<26>;
111 		assigned-clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>;
112 		assigned-clock-parents = <&dpll_gmac_h14x2_ctrl_ck>;
116 		#clock-cells = <0>;
117 		compatible = "ti,gate-clock";
119 		ti,bit-shift = <27>;
134 	max-frequency = <96000000>;