Lines Matching +full:0 +full:x5c000000
61 reg = <0x0 0x48211000 0x0 0x1000>,
62 <0x0 0x48212000 0x0 0x2000>,
63 <0x0 0x48214000 0x0 0x2000>,
64 <0x0 0x48216000 0x0 0x2000>;
73 reg = <0x0 0x48281000 0x0 0x1000>;
79 #size-cells = <0>;
81 cpu0: cpu@0 {
84 reg = <0>;
108 opp-supported-hw = <0xFF 0x01>;
117 opp-supported-hw = <0xFF 0x02>;
124 opp-supported-hw = <0xFF 0x04>;
151 ranges = <0x0 0x0 0x0 0xc0000000>;
152 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
154 reg = <0x0 0x44000000 0x0 0x1000000>,
155 <0x0 0x45000000 0x0 0x1000>;
170 axi@0 {
174 ranges = <0x51000000 0x51000000 0x3000
175 0x0 0x20000000 0x10000000>;
182 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
184 interrupts = <0 232 0x4>, <0 233 0x4>;
188 ranges = <0x81000000 0 0 0x03000 0 0x00010000
189 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
190 bus-range = <0x00 0xff>;
193 linux,pci-domain = <0>;
197 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
198 interrupt-map-mask = <0 0 0 7>;
199 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
200 <0 0 0 2 &pcie1_intc 2>,
201 <0 0 0 3 &pcie1_intc 3>,
202 <0 0 0 4 &pcie1_intc 4>;
203 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
207 #address-cells = <0>;
213 reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>;
215 interrupts = <0 232 0x4>;
222 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
223 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
232 ranges = <0x51800000 0x51800000 0x3000
233 0x0 0x30000000 0x10000000>;
237 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
239 interrupts = <0 355 0x4>, <0 356 0x4>;
243 ranges = <0x81000000 0 0 0x03000 0 0x00010000
244 0x82000000 0 0x30013000 0x13000 0 0xffed000>;
245 bus-range = <0x00 0xff>;
252 interrupt-map-mask = <0 0 0 7>;
253 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
254 <0 0 0 2 &pcie2_intc 2>,
255 <0 0 0 3 &pcie2_intc 3>,
256 <0 0 0 4 &pcie2_intc 4>;
257 ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
260 #address-cells = <0>;
268 reg = <0x40300000 0x80000>;
269 ranges = <0x0 0x40300000 0x80000>;
283 sram-hs@0 {
285 reg = <0x0 0x0>;
298 reg = <0x40400000 0x100000>;
299 ranges = <0x0 0x40400000 0x100000>;
307 reg = <0x40500000 0x100000>;
308 ranges = <0x0 0x40500000 0x100000>;
314 reg = <0x4a0021e0 0xc
315 0x4a00232c 0xc
316 0x4a002380 0x2c
317 0x4a0023C0 0x3c
318 0x4a002564 0x8
319 0x4a002574 0x50>;
327 reg = <0x40d00000 0x100>;
332 reg = <0x4844a000 0x0d1c>;
334 #size-cells = <0>;
340 reg = <0x43300000 0x4>;
342 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPCC_CLKCTRL 0>;
346 ranges = <0x0 0x43300000 0x100000>;
348 edma: dma@0 {
350 reg = <0 0x100000>;
360 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
373 reg = <0x43400000 0x4>;
375 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC0_CLKCTRL 0>;
379 ranges = <0x0 0x43400000 0x100000>;
381 edma_tptc0: dma@0 {
383 reg = <0 0x100000>;
391 reg = <0x43500000 0x4>;
393 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC1_CLKCTRL 0>;
397 ranges = <0x0 0x43500000 0x100000>;
399 edma_tptc1: dma@0 {
401 reg = <0 0x100000>;
409 reg = <0x4e000000 0x800>;
416 reg = <0x58820000 0x10000>;
420 resets = <&prm_ipu 0>, <&prm_ipu 1>;
421 clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
427 reg = <0x55020000 0x10000>;
431 resets = <&prm_core 0>, <&prm_core 1>;
432 clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
438 reg = <0x40800000 0x48000>,
439 <0x40e00000 0x8000>,
440 <0x40f00000 0x8000>;
442 ti,bootreg = <&scm_conf 0x55c 10>;
445 resets = <&prm_dsp1 0>;
446 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
452 reg = <0x40d01000 0x4>,
453 <0x40d01010 0x4>,
454 <0x40d01014 0x4>;
462 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
466 ranges = <0x0 0x40d01000 0x1000>;
470 mmu0_dsp1: mmu@0 {
472 reg = <0x0 0x100>;
474 #iommu-cells = <0>;
475 ti,syscon-mmuconfig = <&dsp1_system 0x0>;
481 reg = <0x40d02000 0x4>,
482 <0x40d02010 0x4>,
483 <0x40d02014 0x4>;
491 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
495 ranges = <0x0 0x40d02000 0x1000>;
499 mmu1_dsp1: mmu@0 {
501 reg = <0x0 0x100>;
503 #iommu-cells = <0>;
504 ti,syscon-mmuconfig = <&dsp1_system 0x1>;
510 reg = <0x58882000 0x4>,
511 <0x58882010 0x4>,
512 <0x58882014 0x4>;
520 clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
526 ranges = <0x0 0x58882000 0x100>;
528 mmu_ipu1: mmu@0 {
530 reg = <0x0 0x100>;
532 #iommu-cells = <0>;
539 reg = <0x55082000 0x4>,
540 <0x55082010 0x4>,
541 <0x55082014 0x4>;
549 clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
555 ranges = <0x0 0x55082000 0x100>;
557 mmu_ipu2: mmu@0 {
559 reg = <0x0 0x100>;
561 #iommu-cells = <0>;
569 #address-cells = <0>;
570 #size-cells = <0>;
575 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
576 <0x4ae06014 0x4>, <0x4a003b20 0xc>,
577 <0x4ae0c158 0x4>;
581 ti,tranxdone-status-mask = <0x80>;
583 ti,ldovbb-override-mask = <0x400>;
585 ti,ldovbb-vset-mask = <0x1F>;
593 1060000 0 0x0 0 0x02000000 0x01F00000
594 1160000 0 0x4 0 0x02000000 0x01F00000
595 1210000 0 0x8 0 0x02000000 0x01F00000
602 #address-cells = <0>;
603 #size-cells = <0>;
608 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
609 <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
610 <0x4a002470 0x4>;
614 ti,tranxdone-status-mask = <0x40000000>;
616 ti,ldovbb-override-mask = <0x400>;
618 ti,ldovbb-vset-mask = <0x1F>;
626 1055000 0 0x0 0 0x02000000 0x01F00000
627 1150000 0 0x4 0 0x02000000 0x01F00000
628 1250000 0 0x8 0 0x02000000 0x01F00000
635 #address-cells = <0>;
636 #size-cells = <0>;
641 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
642 <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
643 <0x4a00246c 0x4>;
647 ti,tranxdone-status-mask = <0x20000000>;
649 ti,ldovbb-override-mask = <0x400>;
651 ti,ldovbb-vset-mask = <0x1F>;
659 1055000 0 0x0 0 0x02000000 0x01F00000
660 1150000 0 0x4 0 0x02000000 0x01F00000
661 1250000 0 0x8 0 0x02000000 0x01F00000
668 #address-cells = <0>;
669 #size-cells = <0>;
674 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
675 <0x4ae06010 0x4>, <0x4a003b08 0xc>,
676 <0x4ae0c154 0x4>;
680 ti,tranxdone-status-mask = <0x10000000>;
682 ti,ldovbb-override-mask = <0x400>;
684 ti,ldovbb-vset-mask = <0x1F>;
692 1090000 0 0x0 0 0x02000000 0x01F00000
693 1210000 0 0x4 0 0x02000000 0x01F00000
694 1280000 0 0x8 0 0x02000000 0x01F00000
700 reg = <0x4b300000 0x100>,
701 <0x5c000000 0x4000000>;
703 syscon-chipselects = <&scm_conf 0x558>;
705 #size-cells = <0>;
717 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
723 ports-implemented = <0x1>;
731 reg = <0x50000000 0x37c>; /* device IO registers */
733 dmas = <&edma_xbar 4 0>;
748 reg = <0x5600fe00 0x4>,
749 <0x5600fe10 0x4>;
757 clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>;
761 ranges = <0 0x56000000 0x2000000>;
766 reg = <0x4a002a48 0x130>;
773 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
775 ti,irqs-safe-map = <0>;
780 reg = <0x58000000 4>,
781 <0x58000014 4>;
784 clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 0>,
791 ranges = <0 0x58000000 0x800000>;
793 dss: dss@0 {
799 syscon-pll-ctrl = <&scm_conf 0x538>;
802 ranges = <0 0 0x800000>;
806 reg = <0x1000 0x4>,
807 <0x1010 0x4>,
808 <0x1014 0x4>;
825 ranges = <0 0x1000 0x1000>;
827 dispc@0 {
829 reg = <0 0x1000>;
834 syscon-pol = <&scm_conf 0x534>;
840 reg = <0x40000 0x4>,
841 <0x40010 0x4>;
853 ranges = <0 0x40000 0x40000>;
855 hdmi: encoder@0 {
857 reg = <0 0x200>,
858 <0x200 0x80>,
859 <0x300 0x80>,
860 <0x20000 0x19000>;
876 reg = <0x4b500080 0x4>,
877 <0x4b500084 0x4>,
878 <0x4b500088 0x4>;
888 clocks = <&l4sec_clkctrl DRA7_L4SEC_AES1_CLKCTRL 0>;
892 ranges = <0x0 0x4b500000 0x1000>;
894 aes1: aes@0 {
896 reg = <0 0xa0>;
898 dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
907 reg = <0x4b700080 0x4>,
908 <0x4b700084 0x4>,
909 <0x4b700088 0x4>;
919 clocks = <&l4sec_clkctrl DRA7_L4SEC_AES2_CLKCTRL 0>;
923 ranges = <0x0 0x4b700000 0x1000>;
925 aes2: aes@0 {
927 reg = <0 0xa0>;
929 dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
938 reg = <0x4b101100 0x4>,
939 <0x4b101110 0x4>,
940 <0x4b101114 0x4>;
949 clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM_CLKCTRL 0>;
953 ranges = <0x0 0x4b101000 0x1000>;
955 sham: sham@0 {
957 reg = <0 0x300>;
959 dmas = <&edma_xbar 119 0>;
968 reg = <0x4a003b20 0xc>;
971 1060000 0x0
972 1160000 0x4
973 1210000 0x8
992 coefficients = <0 2000>;
996 coefficients = <0 2000>;
1000 coefficients = <0 2000>;
1004 coefficients = <0 2000>;
1008 coefficients = <0 2000>;
1037 reg = <0x400 0x100>;
1043 reg = <0x500 0x100>;
1049 reg = <0x700 0x100>;
1055 reg = <0xf00 0x100>;
1060 reg = <0x1b00 0x40>;
1066 reg = <0x1b40 0x40>;
1071 reg = <0x1b80 0x40>;
1076 reg = <0x1bc0 0x40>;
1081 reg = <0x1c00 0x60>;
1089 timer@0 {
1099 timer@0 {
1108 timer@0 {