Lines Matching full:ipu_clkctrl

1562 			clocks = <&ipu_clkctrl DRA7_IPU_UART6_CLKCTRL 0>;
1816 			clocks = <&ipu_clkctrl DRA7_IPU_I2C5_CLKCTRL 0>;
2728 			clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>,
2729 				 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
2730 				 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>;
2747 				clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>,
2748 					 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
2749 					 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>;
2784 					 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
3300 			clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 0>;
3309 				clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 24>, <&timer_sys_clk_div>;
3327 			clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 0>;
3336 				clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 24>, <&timer_sys_clk_div>;
3354 			clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 0>;
3363 				clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 24>, <&timer_sys_clk_div>;
3381 			clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 0>;
3390 				clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 24>, <&timer_sys_clk_div>;