Lines Matching +full:primecell +full:- +full:periphid
1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/soc/bcm2835-pm.h>
10 #address-cells = <2>;
11 #size-cells = <1>;
13 interrupt-parent = <&gicv2>;
16 compatible = "brcm,bcm2711-vc5";
20 clk_27MHz: clk-27M {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <27000000>;
24 clock-output-names = "27MHz-clock";
27 clk_108MHz: clk-108M {
28 #clock-cells = <0>;
29 compatible = "fixed-clock";
30 clock-frequency = <108000000>;
31 clock-output-names = "108MHz-clock";
38 * BCM2711-specific peripherals
39 * ARM-local peripherals
44 /* Emulate a contiguous 30-bit address range for DMA */
45 dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>;
48 * This node is the provider for the enable-method for
52 compatible = "brcm,bcm2836-l1-intc";
56 gicv2: interrupt-controller@40041000 {
57 interrupt-controller;
58 #interrupt-cells = <3>;
59 compatible = "arm,gic-400";
68 avs_monitor: avs-monitor@7d5d2000 {
69 compatible = "brcm,bcm2711-avs-monitor",
70 "syscon", "simple-mfd";
74 compatible = "brcm,bcm2711-thermal";
75 #thermal-sensor-cells = <0>;
80 compatible = "brcm,bcm2835-dma";
89 /* DMA lite 7 - 10 */
94 interrupt-names = "dma0",
105 #dma-cells = <1>;
106 brcm,dma-channel-mask = <0x07f5>;
110 compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
111 #power-domain-cells = <1>;
112 #reset-cells = <1>;
120 clock-names = "v3d", "peri_image", "h264", "isp";
121 system-power-controller;
125 compatible = "brcm,bcm2711-rng200";
130 compatible = "arm,pl011", "arm,primecell";
135 clock-names = "uartclk", "apb_pclk";
136 arm,primecell-periphid = <0x00241011>;
141 compatible = "arm,pl011", "arm,primecell";
146 clock-names = "uartclk", "apb_pclk";
147 arm,primecell-periphid = <0x00241011>;
152 compatible = "arm,pl011", "arm,primecell";
157 clock-names = "uartclk", "apb_pclk";
158 arm,primecell-periphid = <0x00241011>;
163 compatible = "arm,pl011", "arm,primecell";
168 clock-names = "uartclk", "apb_pclk";
169 arm,primecell-periphid = <0x00241011>;
174 compatible = "brcm,bcm2835-spi";
178 #address-cells = <1>;
179 #size-cells = <0>;
184 compatible = "brcm,bcm2835-spi";
188 #address-cells = <1>;
189 #size-cells = <0>;
194 compatible = "brcm,bcm2835-spi";
198 #address-cells = <1>;
199 #size-cells = <0>;
204 compatible = "brcm,bcm2835-spi";
208 #address-cells = <1>;
209 #size-cells = <0>;
214 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
218 #address-cells = <1>;
219 #size-cells = <0>;
224 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
228 #address-cells = <1>;
229 #size-cells = <0>;
234 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
238 #address-cells = <1>;
239 #size-cells = <0>;
244 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
248 #address-cells = <1>;
249 #size-cells = <0>;
254 compatible = "brcm,bcm2711-pixelvalve0";
261 compatible = "brcm,bcm2711-pixelvalve1";
268 compatible = "brcm,bcm2711-pixelvalve2";
275 compatible = "brcm,bcm2835-pwm";
278 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
279 assigned-clock-rates = <10000000>;
280 #pwm-cells = <2>;
285 compatible = "brcm,bcm2711-pixelvalve4";
292 compatible = "brcm,bcm2711-hvs";
298 compatible = "brcm,bcm2711-pixelvalve3";
305 compatible = "brcm,brcm2711-dvp";
308 #clock-cells = <1>;
309 #reset-cells = <1>;
313 compatible = "brcm,bcm2711-hdmi0";
323 reg-names = "hdmi",
332 clock-names = "hdmi", "bvb", "audio", "cec";
336 dma-names = "audio-rx";
341 compatible = "brcm,bcm2711-hdmi-i2c";
343 reg-names = "bsc", "auto-i2c";
344 clock-frequency = <97500>;
349 compatible = "brcm,bcm2711-hdmi1";
359 reg-names = "hdmi",
369 clock-names = "hdmi", "bvb", "audio", "cec";
372 dma-names = "audio-rx";
377 compatible = "brcm,bcm2711-hdmi-i2c";
379 reg-names = "bsc", "auto-i2c";
380 clock-frequency = <97500>;
389 * so, it'll edit the dma-ranges property below accordingly.
392 compatible = "simple-bus";
393 #address-cells = <2>;
394 #size-cells = <1>;
397 dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>;
400 compatible = "brcm,bcm2711-emmc2";
408 arm-pmu {
409 compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3";
414 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
418 compatible = "arm,armv8-timer";
428 arm,cpu-registers-not-fw-configured;
432 #address-cells = <1>;
433 #size-cells = <0>;
434 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
436 /* Source for d/i-cache-line-size and d/i-cache-sets
438 * /Level-1-Memory-System/About-the-L1-memory-system?lang=en
439 * Source for d/i-cache-size
445 compatible = "arm,cortex-a72";
447 enable-method = "spin-table";
448 cpu-release-addr = <0x0 0x000000d8>;
449 d-cache-size = <0x8000>;
450 d-cache-line-size = <64>;
451 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
452 i-cache-size = <0xc000>;
453 i-cache-line-size = <64>;
454 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
455 next-level-cache = <&l2>;
460 compatible = "arm,cortex-a72";
462 enable-method = "spin-table";
463 cpu-release-addr = <0x0 0x000000e0>;
464 d-cache-size = <0x8000>;
465 d-cache-line-size = <64>;
466 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
467 i-cache-size = <0xc000>;
468 i-cache-line-size = <64>;
469 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
470 next-level-cache = <&l2>;
475 compatible = "arm,cortex-a72";
477 enable-method = "spin-table";
478 cpu-release-addr = <0x0 0x000000e8>;
479 d-cache-size = <0x8000>;
480 d-cache-line-size = <64>;
481 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
482 i-cache-size = <0xc000>;
483 i-cache-line-size = <64>;
484 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
485 next-level-cache = <&l2>;
490 compatible = "arm,cortex-a72";
492 enable-method = "spin-table";
493 cpu-release-addr = <0x0 0x000000f0>;
494 d-cache-size = <0x8000>;
495 d-cache-line-size = <64>;
496 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
497 i-cache-size = <0xc000>;
498 i-cache-line-size = <64>;
499 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
500 next-level-cache = <&l2>;
503 /* Source for d/i-cache-line-size and d/i-cache-sets
505 * /Level-2-Memory-System/About-the-L2-memory-system?lang=en
506 * Source for d/i-cache-size
510 l2: l2-cache0 {
512 cache-size = <0x100000>;
513 cache-line-size = <64>;
514 cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set
515 cache-level = <2>;
520 compatible = "simple-bus";
521 #address-cells = <2>;
522 #size-cells = <1>;
528 compatible = "brcm,bcm2711-pcie";
531 #address-cells = <3>;
532 #interrupt-cells = <1>;
533 #size-cells = <2>;
536 interrupt-names = "pcie", "msi";
537 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
538 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
546 msi-controller;
547 msi-parent = <&pcie0>;
556 dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
558 brcm,enable-ssc;
562 compatible = "brcm,bcm2711-genet-v5";
564 #address-cells = <0x1>;
565 #size-cells = <0x1>;
571 compatible = "brcm,genet-mdio-v5";
573 reg-names = "mdio";
574 #address-cells = <0x1>;
575 #size-cells = <0x0>;
582 clock-frequency = <54000000>;
586 compatible = "brcm,bcm2711-cprman";
590 coefficients = <(-487) 410040>;
591 thermal-sensors = <&thermal>;
603 compatible = "brcm,bcm2711-gpio";
609 gpio-ranges = <&gpio 0 0 58>;
612 pin-gpclk {
615 bias-disable;
619 pin-gpclk {
622 bias-disable;
626 pin-gpclk {
629 bias-disable;
634 pin-sda {
637 bias-pull-up;
639 pin-scl {
642 bias-disable;
646 pin-sda {
649 bias-pull-up;
651 pin-scl {
654 bias-disable;
658 pin-sda {
661 bias-pull-up;
663 pin-scl {
666 bias-disable;
670 pin-sda {
673 bias-pull-up;
675 pin-scl {
678 bias-disable;
682 pin-sda {
685 bias-pull-up;
687 pin-scl {
690 bias-disable;
694 pin-sda {
697 bias-pull-up;
699 pin-scl {
702 bias-disable;
706 pin-sda {
709 bias-pull-up;
711 pin-scl {
714 bias-disable;
718 pin-sda {
721 bias-pull-up;
723 pin-scl {
726 bias-disable;
730 pin-sda {
733 bias-pull-up;
735 pin-scl {
738 bias-disable;
742 pin-sda {
745 bias-pull-up;
747 pin-scl {
750 bias-disable;
754 pins-i2c-slave {
764 pins-jtag {
776 pins-mii {
785 pins-mii {
795 pins-pcm {
805 pin-pwm {
808 bias-disable;
812 pin-pwm {
815 bias-disable;
819 pin-pwm {
822 bias-disable;
826 pin-pwm {
829 bias-disable;
833 pin-pwm {
836 bias-disable;
840 pin-pwm {
843 bias-disable;
847 pin-pwm {
850 bias-disable;
854 pin-pwm {
857 bias-disable;
861 pin-pwm {
864 bias-disable;
869 pin-start-stop {
873 pin-rx-ok {
879 pin-irq {
885 pin-irq {
891 pins-mdio {
898 pins-mdio {
906 pins-spi {
915 pins-spi {
925 pins-spi {
934 pins-spi {
943 pins-spi {
952 pins-spi {
962 pin-tx {
965 bias-disable;
967 pin-rx {
970 bias-pull-up;
974 pin-cts {
977 bias-pull-up;
979 pin-rts {
982 bias-disable;
986 pin-tx {
989 bias-disable;
991 pin-rx {
994 bias-pull-up;
998 pin-cts {
1001 bias-pull-up;
1003 pin-rts {
1006 bias-disable;
1010 pin-tx {
1013 bias-disable;
1015 pin-rx {
1018 bias-pull-up;
1022 pin-cts {
1025 bias-pull-up;
1027 pin-rts {
1030 bias-disable;
1034 pin-tx {
1037 bias-disable;
1039 pin-rx {
1042 bias-pull-up;
1046 pin-cts {
1049 bias-pull-up;
1051 pin-rts {
1054 bias-disable;
1060 #address-cells = <2>;
1069 alloc-ranges = <0x0 0x00000000 0x40000000>;
1073 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
1078 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";