Lines Matching +full:0 +full:x200
42 #size-cells = <0>;
44 cpu@0 {
47 reg = <0>;
53 reg = <0x20000000 0x04000000>;
59 #clock-cells = <0>;
60 clock-frequency = <0>;
65 #clock-cells = <0>;
66 clock-frequency = <0>;
71 #clock-cells = <0>;
78 reg = <0x00300000 0x10000>;
81 ranges = <0 0x00300000 0x10000>;
92 reg = <0x00500000 0x1000>;
95 pinctrl-0 = <&pinctrl_fb>;
107 reg = <0x10000000 0x80000000>;
108 ranges = <0x0 0x0 0x10000000 0x10000000
109 0x1 0x0 0x20000000 0x10000000
110 0x2 0x0 0x30000000 0x10000000
111 0x3 0x0 0x40000000 0x10000000
112 0x4 0x0 0x50000000 0x10000000
113 0x5 0x0 0x60000000 0x10000000>;
135 #size-cells = <0>;
136 reg = <0xfffa0000 0x100>;
137 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 0>,
138 <17 IRQ_TYPE_LEVEL_HIGH 0>,
139 <18 IRQ_TYPE_LEVEL_HIGH 0>;
146 reg = <0xfffa4000 0x600>;
147 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
149 #size-cells = <0>;
158 reg = <0xfffa8000 0x100>;
161 #size-cells = <0>;
168 reg = <0xfffac000 0x100>;
171 #size-cells = <0>;
177 reg = <0xfffb0000 0x200>;
182 pinctrl-0 = <&pinctrl_usart0>;
190 reg = <0xfffb4000 0x200>;
195 pinctrl-0 = <&pinctrl_usart1>;
203 reg = <0xfffb8000 0x200>;
208 pinctrl-0 = <&pinctrl_usart2>;
216 reg = <0xfffbc000 0x200>;
221 pinctrl-0 = <&pinctrl_usart3>;
229 reg = <0xfffc0000 0x4000>;
232 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
238 reg = <0xfffc4000 0x4000>;
241 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
247 reg = <0xfffc8000 0x300>;
257 #size-cells = <0>;
259 reg = <0xfffcc000 0x200>;
262 pinctrl-0 = <&pinctrl_spi0>;
270 #size-cells = <0>;
272 reg = <0xfffd0000 0x100>;
273 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
277 atmel,adc-channels-used = <0x3f>;
286 trigger-value = <0x1>;
292 trigger-value = <0x2>;
298 trigger-value = <0x3>;
304 trigger-value = <0x6>;
310 reg = <0x00600000 0x100000>,
311 <0xfffd4000 0x4000>;
320 reg = <0xffffe600 0x200>;
321 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
329 reg = <0xffffea00 0x200>;
334 reg = <0xffffec00 0x200>;
339 reg = <0xffffee00 0x200>;
346 reg = <0xfffff000 0x200>;
352 reg = <0xfffff200 0x200>;
355 pinctrl-0 = <&pinctrl_dbgu>;
365 ranges = <0xfffff400 0xfffff400 0x800>;
369 <0xffffffff 0xe05c6738>, /* pioA */
370 <0xffffffff 0x0000c780>, /* pioB */
371 <0xffffffff 0xe3ffff0e>, /* pioC */
372 <0x003fffff 0x0001ff3c>; /* pioD */
376 pinctrl_adc0_ts: adc0_ts-0 {
384 pinctrl_adc0_ad0: adc0_ad0-0 {
388 pinctrl_adc0_ad1: adc0_ad1-0 {
392 pinctrl_adc0_ad2: adc0_ad2-0 {
396 pinctrl_adc0_ad3: adc0_ad3-0 {
400 pinctrl_adc0_ad4: adc0_ad4-0 {
404 pinctrl_adc0_ad5: adc0_ad5-0 {
408 pinctrl_adc0_adtrg: adc0_adtrg-0 {
414 pinctrl_dbgu: dbgu-0 {
422 pinctrl_ebi_addr_nand: ebi-addr-0 {
430 pinctrl_fb: fb-0 {
457 pinctrl_i2c_gpio0: i2c_gpio0-0 {
465 pinctrl_i2c_gpio1: i2c_gpio1-0 {
473 pinctrl_mmc0_clk: mmc0_clk-0 {
478 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
480 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
484 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
493 pinctrl_nand_rb: nand-rb-0 {
498 pinctrl_nand_cs: nand-cs-0 {
503 pinctrl_nand_oe_we: nand-oe-we-0 {
511 pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 {
523 pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 {
535 pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 {
547 pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 {
557 pinctrl_spi0: spi0-0 {
566 pinctrl_ssc0_tx: ssc0_tx-0 {
569 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE>,
573 pinctrl_ssc0_rx: ssc0_rx-0 {
582 pinctrl_ssc1_tx: ssc1_tx-0 {
589 pinctrl_ssc1_rx: ssc1_rx-0 {
598 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
602 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
606 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
610 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
614 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
618 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
622 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
626 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
630 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
636 pinctrl_usart0: usart0-0 {
642 pinctrl_usart0_rts: usart0_rts-0 {
647 pinctrl_usart0_cts: usart0_cts-0 {
652 pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
658 pinctrl_usart0_dcd: usart0_dcd-0 {
663 pinctrl_usart0_ri: usart0_ri-0 {
668 pinctrl_usart0_sck: usart0_sck-0 {
675 pinctrl_usart1: usart1-0 {
681 pinctrl_usart1_rts: usart1_rts-0 {
686 pinctrl_usart1_cts: usart1_cts-0 {
691 pinctrl_usart1_sck: usart1_sck-0 {
698 pinctrl_usart2: usart2-0 {
704 pinctrl_usart2_rts: usart2_rts-0 {
709 pinctrl_usart2_cts: usart2_cts-0 {
714 pinctrl_usart2_sck: usart2_sck-0 {
721 pinctrl_usart3: usart3-0 {
723 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
727 pinctrl_usart3_rts: usart3_rts-0 {
732 pinctrl_usart3_cts: usart3_cts-0 {
737 pinctrl_usart3_sck: usart3_sck-0 {
745 reg = <0xfffff400 0x200>;
756 reg = <0xfffff600 0x200>;
767 reg = <0xfffff800 0x200>;
778 reg = <0xfffffa00 0x200>;
790 reg = <0xfffffc00 0x100>;
799 reg = <0xfffffd00 0x10>;
805 reg = <0xfffffd10 0x10>;
811 reg = <0xfffffd30 0xf>;
818 reg = <0xfffffd40 0x10>;
826 reg = <0xfffffd50 0x4>;
828 #clock-cells = <0>;
833 reg = <0xfffffd20 0x10>;
841 reg = <0xfffffd60 0x10>;
847 reg = <0xfffffe00 0x40>;
856 i2c-gpio-0 {
864 #size-cells = <0>;
866 pinctrl-0 = <&pinctrl_i2c_gpio0>;
878 #size-cells = <0>;
880 pinctrl-0 = <&pinctrl_i2c_gpio1>;