boot/dts/armada-xp-mv78230.dtsi

26 		#size-cells = <0>;
29 		cpu@0 {
32 			reg = <0>;
33 			clocks = <&cpuclk 0>;
48 		 * MV78230 has 2 PCIe units Gen2.0: One unit can be
61 			bus-range = <0x00 0xff>;
64 			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
65 				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
66 				0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
67 				0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
68 				0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000   /* Port 1.0 registers */
69 				0x82000000 0x1 0       MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
70 				0x81000000 0x1 0       MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
71 				0x82000000 0x2 0       MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
72 				0x81000000 0x2 0       MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO  */
73 				0x82000000 0x3 0       MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
74 				0x81000000 0x3 0       MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO  */
75 				0x82000000 0x4 0       MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
76 				0x81000000 0x4 0       MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */
77 				0x82000000 0x5 0       MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
78 				0x81000000 0x5 0       MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO  */>;
80 			pcie1: pcie@1,0 {
82 				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
83 				reg = <0x0800 0 0 0 0>;
87 				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
88 					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
89 				bus-range = <0x00 0xff>;
90 				interrupt-map-mask = <0 0 0 0>;
91 				interrupt-map = <0 0 0 0 &mpic 58>;
92 				marvell,pcie-port = <0>;
93 				marvell,pcie-lane = <0>;
98 			pcie2: pcie@2,0 {
100 				assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
101 				reg = <0x1000 0 0 0 0>;
105 				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
106 					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
107 				bus-range = <0x00 0xff>;
108 				interrupt-map-mask = <0 0 0 0>;
109 				interrupt-map = <0 0 0 0 &mpic 59>;
110 				marvell,pcie-port = <0>;
116 			pcie3: pcie@3,0 {
118 				assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
119 				reg = <0x1800 0 0 0 0>;
123 				ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
124 					  0x81000000 0 0 0x81000000 0x3 0 1 0>;
125 				bus-range = <0x00 0xff>;
126 				interrupt-map-mask = <0 0 0 0>;
127 				interrupt-map = <0 0 0 0 &mpic 60>;
128 				marvell,pcie-port = <0>;
134 			pcie4: pcie@4,0 {
136 				assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
137 				reg = <0x2000 0 0 0 0>;
141 				ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
142 					  0x81000000 0 0 0x81000000 0x4 0 1 0>;
143 				bus-range = <0x00 0xff>;
144 				interrupt-map-mask = <0 0 0 0>;
145 				interrupt-map = <0 0 0 0 &mpic 61>;
146 				marvell,pcie-port = <0>;
152 			pcie5: pcie@5,0 {
154 				assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
155 				reg = <0x2800 0 0 0 0>;
159 				ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
160 					  0x81000000 0 0 0x81000000 0x5 0 1 0>;
161 				bus-range = <0x00 0xff>;
162 				interrupt-map-mask = <0 0 0 0>;
163 				interrupt-map = <0 0 0 0 &mpic 62>;
165 				marvell,pcie-lane = <0>;
175 				reg = <0x18100 0x40>, <0x181c0 0x08>;
184 				clocks = <&coreclk 0>;
190 				reg = <0x18140 0x40>, <0x181c8 0x08>;
199 				clocks = <&coreclk 0>;