Lines Matching +full:0 +full:x56000000
50 #size-cells = <0>;
51 cpu@0 {
55 reg = <0>;
89 opp-supported-hw = <0x06 0x0010>;
96 opp-supported-hw = <0x01 0x00FF>;
103 opp-supported-hw = <0x06 0x0020>;
110 opp-supported-hw = <0x01 0xFFFF>;
116 opp-supported-hw = <0x06 0x0040>;
122 opp-supported-hw = <0x01 0xFFFF>;
128 opp-supported-hw = <0x06 0x0080>;
134 opp-supported-hw = <0x01 0xFFFF>;
140 opp-supported-hw = <0x06 0x0100>;
146 opp-supported-hw = <0x04 0x0200>;
153 reg = <0x4b000000 0x1000000>;
188 reg = <0x100000 0x4000>,
189 <0x180000 0x2000>;
208 reg = <0x48200000 0x1000>;
213 reg = <0x49000000 0x4>;
215 clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>;
219 ranges = <0x0 0x49000000 0x10000>;
221 edma: dma@0 {
223 reg = <0 0x10000>;
232 <&edma_tptc2 0>;
240 reg = <0x49800000 0x4>,
241 <0x49800010 0x4>;
247 clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>;
251 ranges = <0x0 0x49800000 0x100000>;
253 edma_tptc0: dma@0 {
255 reg = <0 0x100000>;
263 reg = <0x49900000 0x4>,
264 <0x49900010 0x4>;
270 clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>;
274 ranges = <0x0 0x49900000 0x100000>;
276 edma_tptc1: dma@0 {
278 reg = <0 0x100000>;
286 reg = <0x49a00000 0x4>,
287 <0x49a00010 0x4>;
293 clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>;
297 ranges = <0x0 0x49a00000 0x100000>;
299 edma_tptc2: dma@0 {
301 reg = <0 0x100000>;
309 reg = <0x478102fc 0x4>,
310 <0x47810110 0x4>,
311 <0x47810114 0x4>;
321 clocks = <&l3s_clkctrl AM3_L3S_MMC3_CLKCTRL 0>;
325 ranges = <0x0 0x47810000 0x1000>;
327 mmc3: mmc@0 {
331 reg = <0x0 0x1000>;
338 reg = <0x47400000 0x4>,
339 <0x47400010 0x4>;
350 clocks = <&l3s_clkctrl AM3_L3S_USB_OTG_HS_CLKCTRL 0>;
354 ranges = <0x0 0x47400000 0x8000>;
358 reg = <0x1300 0x100>;
361 #phy-cells = <0>;
366 reg = <0x1400 0x400>,
367 <0x1000 0x200>;
379 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
380 &cppi41dma 2 0 &cppi41dma 3 0
381 &cppi41dma 4 0 &cppi41dma 5 0
382 &cppi41dma 6 0 &cppi41dma 7 0
383 &cppi41dma 8 0 &cppi41dma 9 0
384 &cppi41dma 10 0 &cppi41dma 11 0
385 &cppi41dma 12 0 &cppi41dma 13 0
386 &cppi41dma 14 0 &cppi41dma 0 1
405 reg = <0x1b00 0x100>;
408 #phy-cells = <0>;
413 reg = <0x1c00 0x400>,
414 <0x1800 0x200>;
425 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
426 &cppi41dma 17 0 &cppi41dma 18 0
427 &cppi41dma 19 0 &cppi41dma 20 0
428 &cppi41dma 21 0 &cppi41dma 22 0
429 &cppi41dma 23 0 &cppi41dma 24 0
430 &cppi41dma 25 0 &cppi41dma 26 0
431 &cppi41dma 27 0 &cppi41dma 28 0
432 &cppi41dma 29 0 &cppi41dma 15 1
451 reg = <0x0000 0x1000>,
452 <0x2000 0x1000>,
453 <0x3000 0x1000>,
454 <0x4000 0x4000>;
466 reg = <0x40300000 0x10000>; /* 64k */
467 ranges = <0x0 0x40300000 0x10000>;
471 pm_sram_code: pm-code-sram@0 {
473 reg = <0x0 0x1000>;
479 reg = <0x1000 0x1000>;
486 reg = <0x4c000000 0x1000000>;
498 reg = <0x50000000 0x2000>;
500 dmas = <&edma 52 0>;
515 reg = <0x53100100 0x4>,
516 <0x53100110 0x4>,
517 <0x53100114 0x4>;
526 clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>;
530 ranges = <0x0 0x53100000 0x1000>;
532 sham: sham@0 {
534 reg = <0 0x200>;
536 dmas = <&edma 36 0>;
543 reg = <0x53500080 0x4>,
544 <0x53500084 0x4>,
545 <0x53500088 0x4>;
555 clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>;
559 ranges = <0x0 0x53500000 0x1000>;
561 aes: aes@0 {
563 reg = <0 0xa0>;
565 dmas = <&edma 6 0>,
566 <&edma 5 0>;
573 reg = <0x5600fe00 0x4>,
574 <0x5600fe10 0x4>;
582 clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>;
585 resets = <&prm_gfx 0>;
589 ranges = <0 0x56000000 0x1000000>;
605 reg = <0xc00 0x100>;
611 reg = <0xd00 0x100>;
617 reg = <0xf00 0x100>;
623 reg = <0x1100 0x100>;
624 #power-domain-cells = <0>;
633 timer@0 {
643 timer@0 {