Lines Matching refs:mcr
32 mcr p14, 0, \ch, c0, c5, 0
38 mcr p14, 0, \ch, c8, c0, 0
44 mcr p14, 0, \ch, c1, c0, 0
143 mcr p15, 0, \reg, c1, c0, 0 @ write SCTLR
716 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
717 mcr p15, 0, r0, c6, c7, 1
720 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
721 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
722 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
725 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
726 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
729 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
730 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
731 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
737 mcr p15, 0, r0, c1, c0, 0 @ write control reg
740 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
741 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
746 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
749 mcr p15, 0, r0, c2, c0, 0 @ cache on
750 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
753 mcr p15, 0, r0, c5, c0, 0 @ access permission
756 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
766 mcr p15, 0, r0, c1, c0, 0 @ write control reg
769 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
825 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
831 mcr p15, 7, r0, c15, c0, 0
840 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
841 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
848 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
861 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
883 mcr p15, 0, r0, c7, c5, 4 @ ISB
884 mcr p15, 0, r0, c1, c0, 0 @ load control register
887 mcr p15, 0, r0, c7, c5, 4 @ ISB
895 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
896 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
897 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
902 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
911 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
912 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
915 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
1147 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
1149 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
1150 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
1151 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
1157 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
1159 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1166 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1168 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
1169 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
1180 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1183 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
1185 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
1186 mcr p15, 0, r0, c7, c10, 4 @ DSB
1187 mcr p15, 0, r0, c7, c5, 4 @ ISB
1212 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
1215 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
1223 mcr p15, 0, ip, c7, c10, 4 @ drain WB
1230 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
1231 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1232 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1239 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
1241 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1252 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
1262 mcr p15, 0, r0, c7, c14, 1 @ Dcache clean/invalidate by VA
1266 mcr p15, 0, r10, c7, c10, 4 @ DSB
1267 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
1268 mcr p15, 0, r10, c7, c10, 4 @ DSB
1269 mcr p15, 0, r10, c7, c5, 4 @ ISB
1277 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
1278 mcr p15, 0, r0, c7, c10, 4 @ drain WB
1310 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1311 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
1312 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1320 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
1433 mcr p15, 4, r0, c1, c0, 0 @ write HSCTLR