Lines Matching refs:c0
32 mcr p14, 0, \ch, c0, c5, 0
38 mcr p14, 0, \ch, c8, c0, 0
44 mcr p14, 0, \ch, c1, c0, 0
139 mrc p15, 0, \reg, c1, c0, 0 @ read SCTLR
143 mcr p15, 0, \reg, c1, c0, 0 @ write SCTLR
681 mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
720 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
721 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
722 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
725 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
726 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
732 mrc p15, 0, r0, c1, c0, 0 @ read control reg
737 mcr p15, 0, r0, c1, c0, 0 @ write control reg
749 mcr p15, 0, r0, c2, c0, 0 @ cache on
750 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
753 mcr p15, 0, r0, c5, c0, 0 @ access permission
756 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
761 mrc p15, 0, r0, c1, c0, 0 @ read control reg
766 mcr p15, 0, r0, c1, c0, 0 @ write control reg
769 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
822 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
825 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
831 mcr p15, 7, r0, c15, c0, 0
842 mrc p15, 0, r0, c1, c0, 0 @ read control reg
856 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
865 mrc p15, 0, r0, c1, c0, 0 @ read control reg
874 mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg
879 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
880 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
881 mcrne p15, 0, r6, c2, c0, 2 @ load ttb control
884 mcr p15, 0, r0, c1, c0, 0 @ load control register
885 mrc p15, 0, r0, c1, c0, 0 @ and read it back
898 mrc p15, 0, r0, c1, c0, 0 @ read control reg
911 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
912 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
915 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
916 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
938 mrc p15, 0, r9, c0, c0 @ get processor ID
1145 mrc p15, 0, r0, c1, c0
1147 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
1155 mrc p15, 0, r0, c1, c0
1157 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
1159 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1164 mrc p15, 0, r0, c1, c0
1166 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1174 mrc p15, 0, r0, c1, c0
1180 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1248 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
1286 mrc p15, 0, r3, c0, c0, 1 @ read cache type
1320 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
1431 mrc p15, 4, r0, c1, c0, 0 @ read HSCTLR
1433 mcr p15, 4, r0, c1, c0, 0 @ write HSCTLR
1461 mrc p15, 4, r1, c1, c0, 0 @ read HSCTLR