Lines Matching full:r0
79 mov r0, \val
84 mov r0, \val
239 mov r0, #0x17 @ angel_SWIreason_EnterSVC
243 safe_svcmode_maskall r0
292 mov r0, pc
293 cmp r0, r4
294 ldrcc r0, .Lheadroom
295 addcc r0, r0, pc
296 cmpcc r4, r0
300 restart: adr r0, LC1
301 ldr sp, [r0]
302 ldr r6, [r0, #4]
303 add sp, sp, r0
304 add r6, r6, r0
372 mov r0, r8
382 cmp r0, #1
383 sub r0, r4, #(TEXT_OFFSET & 0xffff0000)
384 sub r0, r0, #(TEXT_OFFSET & 0x0000ffff)
385 bic r0, r0, #1
386 add r0, r0, #0x100
462 mrs r0, spsr
463 and r0, r0, #MODE_MASK
464 cmp r0, #HYP_MODE
474 0: adr r0, 0b
477 add r0, r0, r1
478 sub r0, r0, r5
479 add r0, r0, r10
504 1: ldmdb r6!, {r0 - r3, r10 - r12, lr}
506 stmdb r9!, {r0 - r3, r10 - r12, lr}
512 mov r0, r9 @ start of relocated zImage
516 badr r0, restart
517 add r0, r0, r6
518 mov pc, r0
521 adr r0, LC0
522 ldmia r0, {r1, r2, r3, r11, r12}
523 sub r0, r0, r1 @ calculate the delta offset
527 * r0 = delta
538 orrs r1, r0, r5
541 add r11, r11, r0
542 add r12, r12, r0
550 add r2, r2, r0
551 add r3, r3, r0
558 add r1, r1, r0 @ This fixes up C references
579 addlo r1, r1, r0 @ table. This fixes up the
585 not_relocated: mov r0, #0
586 1: str r0, [r2], #4 @ clear bss
587 str r0, [r2], #4
588 str r0, [r2], #4
589 str r0, [r2], #4
609 mov r0, r4
617 mov r0, r4 @ start of inflated image
618 add r1, r1, r0 @ end of inflated image
623 mrs r0, spsr @ Get saved CPU boot mode
624 and r0, r0, #MODE_MASK
625 cmp r0, #HYP_MODE @ if not booted in HYP mode...
629 ldr r0, [r12]
630 add r0, r0, r12
665 params: ldr r0, =0x10000100 @ params_phys for RPC
702 * r0, r1, r2, r3, r9, r10, r12 corrupted
715 mov r0, #0x3f @ 4G, the whole
716 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
717 mcr p15, 0, r0, c6, c7, 1
719 mov r0, #0x80 @ PR7
720 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
721 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
722 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
724 mov r0, #0xc000
725 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
726 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
728 mov r0, #0
729 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
730 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
731 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
732 mrc p15, 0, r0, c1, c0, 0 @ read control reg
734 orr r0, r0, #0x002d @ .... .... ..1. 11.1
735 orr r0, r0, #0x1000 @ ...1 .... .... ....
737 mcr p15, 0, r0, c1, c0, 0 @ write control reg
739 mov r0, #0
740 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
741 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
745 mov r0, #0x3f @ 4G, the whole
746 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
748 mov r0, #0x80 @ PR7
749 mcr p15, 0, r0, c2, c0, 0 @ cache on
750 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
752 mov r0, #0xc000
753 mcr p15, 0, r0, c5, c0, 0 @ access permission
755 mov r0, #0
756 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
761 mrc p15, 0, r0, c1, c0, 0 @ read control reg
763 orr r0, r0, #0x000d @ .... .... .... 11.1
765 mov r0, #0
766 mcr p15, 0, r0, c1, c0, 0 @ write control reg
769 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
785 mov r0, r3
786 mov r9, r0, lsr #20
797 str r1, [r0], #4 @ 1:1 mapping
799 teq r0, r2
812 add r0, r3, r2, lsl #2
813 str r1, [r0], #4
815 str r1, [r0]
822 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
823 bic r0, r0, #2 @ A (no unaligned access fault)
824 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
825 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
830 mov r0, #4 @ put dcache in WT mode
831 mcr p15, 7, r0, c15, c0, 0
839 mov r0, #0
840 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
841 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
842 mrc p15, 0, r0, c1, c0, 0 @ read control reg
843 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
844 orr r0, r0, #0x0030
845 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
847 mov r0, #0
848 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
860 mov r0, #0
861 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
863 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
865 mrc p15, 0, r0, c1, c0, 0 @ read control reg
866 bic r0, r0, #1 << 28 @ clear SCTLR.TRE
867 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
868 orr r0, r0, #0x003c @ write buffer
869 bic r0, r0, #2 @ A (no unaligned access fault)
870 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
873 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
875 orrne r0, r0, #1 @ MMU enabled
883 mcr p15, 0, r0, c7, c5, 4 @ ISB
884 mcr p15, 0, r0, c1, c0, 0 @ load control register
885 mrc p15, 0, r0, c1, c0, 0 @ and read it back
886 mov r0, #0
887 mcr p15, 0, r0, c7, c5, 4 @ ISB
894 mov r0, #0
895 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
896 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
897 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
898 mrc p15, 0, r0, c1, c0, 0 @ read control reg
899 orr r0, r0, #0x1000 @ I-cache enable
901 mov r0, #0
902 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
908 orr r0, r0, #0x000d @ Write buffer, mmu
915 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
916 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
917 sub pc, lr, r0, lsr #32 @ properly flush pipeline
1136 * r0, r1, r2, r3, r9, r12 corrupted
1145 mrc p15, 0, r0, c1, c0
1146 bic r0, r0, #0x000d
1147 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
1148 mov r0, #0
1149 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
1150 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
1151 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
1155 mrc p15, 0, r0, c1, c0
1156 bic r0, r0, #0x000d
1157 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
1158 mov r0, #0
1159 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1164 mrc p15, 0, r0, c1, c0
1165 bic r0, r0, #0x000d
1166 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1167 mov r0, #0
1168 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
1169 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
1174 mrc p15, 0, r0, c1, c0
1176 bic r0, r0, #0x0005
1178 bic r0, r0, #0x0004
1180 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1181 mov r0, #0
1183 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
1185 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
1186 mcr p15, 0, r0, c7, c10, 4 @ DSB
1187 mcr p15, 0, r0, c7, c5, 4 @ ISB
1194 * r0 = start address
1257 bic r0, r0, r2 @ round down start to line size
1260 0: cmp r0, r11 @ finished?
1262 mcr p15, 0, r0, c7, c14, 1 @ Dcache clean/invalidate by VA
1263 add r0, r0, r1
1277 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
1278 mcr p15, 0, r0, c7, c10, 4 @ drain WB
1333 @ phex corrupts {r0, r1, r2, r3}
1338 movmi r0, r3
1340 and r2, r0, #15
1341 mov r0, r0, lsr #4
1348 @ puts corrupts {r0, r1, r2, r3}
1350 1: ldrb r2, [r0], #1
1360 teq r0, #0
1363 @ putc corrupts {r0, r1, r2, r3}
1365 mov r2, r0
1366 loadsp r3, r1, r0
1367 mov r0, #0
1370 @ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
1371 memdump: mov r12, r0
1374 2: mov r0, r11, lsl #2
1375 add r0, r0, r12
1378 mov r0, #':'
1380 1: mov r0, #' '
1382 ldr r0, [r12, r11, lsl #2]
1385 and r0, r11, #7
1386 teq r0, #3
1387 moveq r0, #' '
1389 and r0, r11, #7
1391 teq r0, #7
1393 mov r0, #'\n'
1420 mov r0, #0 @ must be 0
1431 mrc p15, 4, r0, c1, c0, 0 @ read HSCTLR
1432 bic r0, r0, #0x5 @ disable MMU and caches
1433 mcr p15, 4, r0, c1, c0, 0 @ write HSCTLR
1438 mov r4, r0 @ preserve image base
1441 adr_l r0, call_cache_fn
1455 mrs r0, cpsr @ get the current mode
1456 msr spsr_cxsf, r0 @ record boot mode
1457 and r0, r0, #MODE_MASK @ are we running in HYP mode?
1458 cmp r0, #HYP_MODE
1475 adr r0, __hyp_reentry_vectors
1476 mcr p15, 4, r0, c12, c0, 0 @ set HYP vector base (HVBAR)
1488 msr spsr_cxsf, r0 @ record boot mode
1493 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
1494 tst r0, #0x1 @ MMU enabled?
1498 mov r0, r8 @ DT start
1502 adr r0, 0f @ switch to our stack
1503 ldr sp, [r0]
1504 add sp, sp, r0