Lines Matching refs:erratum

852 	  fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
861 	  r1p* erratum. If a code sequence containing an ARM/Thumb
878 	  erratum. For very specific sequences of memory operations, it is
892 	  erratum. Any asynchronous access to the L2 cache may encounter a
905 	  (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
918 	  (r2p0..r2p2) erratum. Under certain conditions, specific to the
933 	  r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
943 	  r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
945 	  As a consequence of this erratum, some TLB entries which should be
956 	  (r2p*) erratum. Under very rare conditions, a faulty
970 	  to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
980 	  r3p*) erratum. A speculative memory access may cause a page table walk
991 	  r2p0) erratum. The Store Buffer does not have any automatic draining
1002 	  r0p2 erratum (possible cache data corruption with
1013 	  This option enables the workaround for erratum 764369
1028 	 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
1039 	  option enables the Linux kernel workaround for this erratum
1048 	  (up to r0p4) erratum. In certain rare sequences of code, the
1050 	  workaround disables the loop buffer to avoid the erratum.
1071 	  (all revs) erratum. In very rare timing conditions, a sequence
1081 	  (all revs) erratum. Within rare timing constraints, executing a
1090 	  (all revs) erratum. Under very rare timing conditions, the CPU might
1098 	  (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1110 	  This is identical to Cortex-A12 erratum 852422.  It is a separate
1111 	  config option from the A12 erratum due to the way errata are checked
1118 	  This option enables the workaround for the 857272 Cortex-A17 erratum.
1119 	  This erratum is not known to be fixed in any A17 revision.
1120 	  This is identical to Cortex-A12 erratum 857271.  It is a separate
1121 	  config option from the A12 erratum due to the way errata are checked
1161 	  However, because of this erratum, an L2 set/way cache maintenance