Lines Matching +full:way +full:- +full:select
1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T
6 select ARCH_HAS_BINFMT_FLAT
7 select ARCH_HAS_DEBUG_VIRTUAL if MMU
8 select ARCH_HAS_DEVMEM_IS_ALLOWED
9 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
10 select ARCH_HAS_ELF_RANDOMIZE
11 select ARCH_HAS_FORTIFY_SOURCE
12 select ARCH_HAS_KEEPINITRD
13 select ARCH_HAS_KCOV
14 select ARCH_HAS_MEMBARRIER_SYNC_CORE
15 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
16 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
17 select ARCH_HAS_PHYS_TO_DMA
18 select ARCH_HAS_SETUP_DMA_OPS
19 select ARCH_HAS_SET_MEMORY
20 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
21 select ARCH_HAS_STRICT_MODULE_RWX if MMU && (!ROCKCHIP_MINI_KERNEL || STRICT_KERNEL_RWX)
22 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB
23 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB
24 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
25 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
26 select ARCH_HAVE_CUSTOM_GPIO_H
27 select ARCH_HAS_GCOV_PROFILE_ALL
28 select ARCH_KEEP_MEMBLOCK
29 select ARCH_MIGHT_HAVE_PC_PARPORT
30 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN
31 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
32 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
33 select ARCH_SUPPORTS_ATOMIC_RMW
34 select ARCH_USE_BUILTIN_BSWAP
35 select ARCH_USE_CMPXCHG_LOCKREF
36 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
37 select ARCH_WANT_IPC_PARSE_VERSION
38 select ARCH_WANT_LD_ORPHAN_WARN
39 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
40 select BUILDTIME_TABLE_SORT if MMU
41 select CLONE_BACKWARDS
42 select CPU_PM if SUSPEND || CPU_IDLE
43 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
44 select DMA_DECLARE_COHERENT
45 select DMA_OPS
46 select DMA_REMAP if MMU
47 select EDAC_SUPPORT
48 select EDAC_ATOMIC_SCRUB
49 select GENERIC_ALLOCATOR
50 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
51 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
52 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
53 select GENERIC_IRQ_IPI if SMP
54 select ARCH_WANTS_IRQ_RAW if GENERIC_IRQ_IPI
55 select GENERIC_CPU_AUTOPROBE
56 select GENERIC_EARLY_IOREMAP
57 select GENERIC_IDLE_POLL_SETUP
58 select GENERIC_IRQ_PROBE
59 select GENERIC_IRQ_SHOW
60 select GENERIC_IRQ_SHOW_LEVEL
61 select GENERIC_PCI_IOMAP
62 select GENERIC_SCHED_CLOCK
63 select GENERIC_SMP_IDLE_THREAD
64 select GENERIC_STRNCPY_FROM_USER
65 select GENERIC_STRNLEN_USER
66 select HANDLE_DOMAIN_IRQ
67 select HARDIRQS_SW_RESEND
68 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
69 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
70 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
71 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
72 select HAVE_ARCH_MMAP_RND_BITS if MMU
73 select HAVE_ARCH_SECCOMP
74 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
75 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
76 select HAVE_ARCH_TRACEHOOK
77 select HAVE_ARM_SMCCC if CPU_V7
78 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
79 select HAVE_CONTEXT_TRACKING
80 select HAVE_C_RECORDMCOUNT
81 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
82 select HAVE_DMA_CONTIGUOUS if MMU
83 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
84 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
85 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
86 select HAVE_EXIT_THREAD
87 select HAVE_FAST_GUP if ARM_LPAE
88 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
89 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG
90 select HAVE_FUNCTION_TRACER if !XIP_KERNEL
91 select HAVE_FUTEX_CMPXCHG if FUTEX
92 select HAVE_GCC_PLUGINS
93 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
94 select HAVE_IDE if PCI || ISA || PCMCIA
95 select HAVE_IRQ_TIME_ACCOUNTING
96 select HAVE_KERNEL_GZIP
97 select HAVE_KERNEL_LZ4
98 select HAVE_KERNEL_LZMA
99 select HAVE_KERNEL_LZO
100 select HAVE_KERNEL_XZ
101 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
102 select HAVE_KRETPROBES if HAVE_KPROBES
103 select HAVE_MOD_ARCH_SPECIFIC
104 select HAVE_NMI
105 select HAVE_OPROFILE if HAVE_PERF_EVENTS
106 select HAVE_OPTPROBES if !THUMB2_KERNEL
107 select HAVE_PERF_EVENTS
108 select HAVE_PERF_REGS
109 select HAVE_PERF_USER_STACK_DUMP
110 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE
111 select HAVE_REGS_AND_STACK_ACCESS_API
112 select HAVE_RSEQ
113 select HAVE_STACKPROTECTOR
114 select HAVE_SYSCALL_TRACEPOINTS
115 select HAVE_UID16
116 select HAVE_VIRT_CPU_ACCOUNTING_GEN
117 select IRQ_FORCED_THREADING
118 select MODULES_USE_ELF_REL
119 select NEED_DMA_MAP_STATE
120 select OF_EARLY_FLATTREE if OF
121 select OLD_SIGACTION
122 select OLD_SIGSUSPEND3
123 select PCI_SYSCALL if PCI
124 select PERF_USE_VMALLOC
125 select RTC_LIB
126 select SET_FS
127 select SYS_SUPPORTS_APM_EMULATION
131 The ARM series is a line of low-power-consumption RISC chip designs
133 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
134 manufactured, but legacy ARM-based PC hardware remains popular in
143 select ARM_HAS_SG_CHAIN
144 select NEED_SG_DMA_LENGTH
172 select GENERIC_ALLOCATOR
244 Patch phys-to-virt and virt-to-phys translation functions at
248 This can only be used with non-XIP MMU kernels where the base
258 Select this when mach/io.h is required to provide special
265 Select this when mach/memory.h is required to provide special
294 bool "MMU-based Paged Memory Management Support"
297 Select if you want MMU-based virtualised addressing space
320 select ARCH_FLATMEM_ENABLE
321 select ARCH_SPARSEMEM_ENABLE
322 select ARCH_SELECT_MEMORY_MODEL
323 select ARM_HAS_SG_CHAIN
324 select ARM_PATCH_PHYS_VIRT
325 select AUTO_ZRELADDR
326 select TIMER_OF
327 select COMMON_CLK
328 select GENERIC_CLOCKEVENTS
329 select GENERIC_IRQ_MULTI_HANDLER
330 select HAVE_PCI
331 select PCI_DOMAINS_GENERIC if PCI
332 select SPARSE_IRQ
333 select USE_OF
336 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
338 select ARM_NVIC
339 select AUTO_ZRELADDR
340 select TIMER_OF
341 select COMMON_CLK
342 select CPU_V7M
343 select GENERIC_CLOCKEVENTS
344 select NO_IOPORT_MAP
345 select SPARSE_IRQ
346 select USE_OF
349 bool "EBSA-110"
350 select ARCH_USES_GETTIMEOFFSET
351 select CPU_SA110
352 select ISA
353 select NEED_MACH_IO_H
354 select NEED_MACH_MEMORY_H
355 select NO_IOPORT_MAP
358 from Digital. It has limited hardware on-board, including an
363 bool "EP93xx-based"
364 select ARCH_SPARSEMEM_ENABLE
365 select ARM_AMBA
367 select ARM_VIC
368 select AUTO_ZRELADDR
369 select CLKDEV_LOOKUP
370 select CLKSRC_MMIO
371 select CPU_ARM920T
372 select GENERIC_CLOCKEVENTS
373 select GPIOLIB
374 select HAVE_LEGACY_CLK
380 select CPU_SA110
381 select FOOTBRIDGE
382 select GENERIC_CLOCKEVENTS
383 select HAVE_IDE
384 select NEED_MACH_IO_H if !MMU
385 select NEED_MACH_MEMORY_H
391 bool "IOP32x-based"
393 select CPU_XSCALE
394 select GPIO_IOP
395 select GPIOLIB
396 select NEED_RET_TO_USER
397 select FORCE_PCI
398 select PLAT_IOP
404 bool "IXP4xx-based"
406 select ARCH_HAS_DMA_SET_COHERENT_MASK
407 select ARCH_SUPPORTS_BIG_ENDIAN
408 select CPU_XSCALE
409 select DMABOUNCE if PCI
410 select GENERIC_CLOCKEVENTS
411 select GENERIC_IRQ_MULTI_HANDLER
412 select GPIO_IXP4XX
413 select GPIOLIB
414 select HAVE_PCI
415 select IXP4XX_IRQ
416 select IXP4XX_TIMER
417 select NEED_MACH_IO_H
418 select USB_EHCI_BIG_ENDIAN_DESC
419 select USB_EHCI_BIG_ENDIAN_MMIO
425 select CPU_PJ4
426 select GENERIC_CLOCKEVENTS
427 select GENERIC_IRQ_MULTI_HANDLER
428 select GPIOLIB
429 select HAVE_PCI
430 select MVEBU_MBUS
431 select PINCTRL
432 select PINCTRL_DOVE
433 select PLAT_ORION_LEGACY
434 select SPARSE_IRQ
435 select PM_GENERIC_DOMAINS if PM
440 bool "PXA2xx/PXA3xx-based"
442 select ARCH_MTD_XIP
443 select ARM_CPU_SUSPEND if PM
444 select AUTO_ZRELADDR
445 select COMMON_CLK
446 select CLKSRC_PXA
447 select CLKSRC_MMIO
448 select TIMER_OF
449 select CPU_XSCALE if !CPU_XSC3
450 select GENERIC_CLOCKEVENTS
451 select GENERIC_IRQ_MULTI_HANDLER
452 select GPIO_PXA
453 select GPIOLIB
454 select HAVE_IDE
455 select IRQ_DOMAIN
456 select PLAT_PXA
457 select SPARSE_IRQ
464 select ARCH_ACORN
465 select ARCH_MAY_HAVE_PC_FDC
466 select ARCH_SPARSEMEM_ENABLE
467 select ARM_HAS_SG_CHAIN
468 select CPU_SA110
469 select FIQ
470 select HAVE_IDE
471 select HAVE_PATA_PLATFORM
472 select ISA_DMA_API
473 select NEED_MACH_IO_H
474 select NEED_MACH_MEMORY_H
475 select NO_IOPORT_MAP
477 On the Acorn Risc-PC, Linux can support the internal IDE disk and
478 CD-ROM interface, serial and parallel port, and the floppy drive.
481 bool "SA1100-based"
482 select ARCH_MTD_XIP
483 select ARCH_SPARSEMEM_ENABLE
484 select CLKSRC_MMIO
485 select CLKSRC_PXA
486 select TIMER_OF if OF
487 select COMMON_CLK
488 select CPU_FREQ
489 select CPU_SA1100
490 select GENERIC_CLOCKEVENTS
491 select GENERIC_IRQ_MULTI_HANDLER
492 select GPIOLIB
493 select HAVE_IDE
494 select IRQ_DOMAIN
495 select ISA
496 select NEED_MACH_MEMORY_H
497 select SPARSE_IRQ
503 select ATAGS
504 select CLKSRC_SAMSUNG_PWM
505 select GENERIC_CLOCKEVENTS
506 select GPIO_SAMSUNG
507 select GPIOLIB
508 select GENERIC_IRQ_MULTI_HANDLER
509 select HAVE_S3C2410_I2C if I2C
510 select HAVE_S3C_RTC if RTC_CLASS
511 select NEED_MACH_IO_H
512 select S3C2410_WATCHDOG
513 select SAMSUNG_ATAGS
514 select USE_OF
515 select WATCHDOG
525 select ARCH_OMAP
526 select CLKDEV_LOOKUP
527 select CLKSRC_MMIO
528 select GENERIC_CLOCKEVENTS
529 select GENERIC_IRQ_CHIP
530 select GENERIC_IRQ_MULTI_HANDLER
531 select GPIOLIB
532 select HAVE_IDE
533 select HAVE_LEGACY_CLK
534 select IRQ_DOMAIN
535 select NEED_MACH_IO_H if PCCARD
536 select NEED_MACH_MEMORY_H
537 select SPARSE_IRQ
551 select ARCH_MULTI_V4_V5
552 select CPU_FA526
557 select ARCH_MULTI_V4_V5
558 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
565 select ARCH_MULTI_V4_V5
566 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
575 select ARCH_MULTI_V6_V7
576 select CPU_V6K
579 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
581 select ARCH_MULTI_V6_V7
582 select CPU_V7
583 select HAVE_SMP
587 select MIGHT_HAVE_CACHE_L2X0
591 select ARCH_MULTI_V5
598 select ARM_AMBA
599 select ARM_GIC
600 select ARM_GIC_V2M if PCI
601 select ARM_GIC_V3
602 select ARM_GIC_V3_ITS if PCI
603 select ARM_PSCI
604 select HAVE_ARM_ARCH_TIMER
605 select ARCH_SUPPORTS_BIG_ENDIAN
608 # This is sorted alphabetically by mach-* pathname. However, plat-*
610 # plat- suffix) or along side the corresponding mach-* source.
612 source "arch/arm/mach-actions/Kconfig"
614 source "arch/arm/mach-alpine/Kconfig"
616 source "arch/arm/mach-artpec/Kconfig"
618 source "arch/arm/mach-asm9260/Kconfig"
620 source "arch/arm/mach-aspeed/Kconfig"
622 source "arch/arm/mach-at91/Kconfig"
624 source "arch/arm/mach-axxia/Kconfig"
626 source "arch/arm/mach-bcm/Kconfig"
628 source "arch/arm/mach-berlin/Kconfig"
630 source "arch/arm/mach-clps711x/Kconfig"
632 source "arch/arm/mach-cns3xxx/Kconfig"
634 source "arch/arm/mach-davinci/Kconfig"
636 source "arch/arm/mach-digicolor/Kconfig"
638 source "arch/arm/mach-dove/Kconfig"
640 source "arch/arm/mach-ep93xx/Kconfig"
642 source "arch/arm/mach-exynos/Kconfig"
644 source "arch/arm/mach-footbridge/Kconfig"
646 source "arch/arm/mach-gemini/Kconfig"
648 source "arch/arm/mach-highbank/Kconfig"
650 source "arch/arm/mach-hisi/Kconfig"
652 source "arch/arm/mach-imx/Kconfig"
654 source "arch/arm/mach-integrator/Kconfig"
656 source "arch/arm/mach-iop32x/Kconfig"
658 source "arch/arm/mach-ixp4xx/Kconfig"
660 source "arch/arm/mach-keystone/Kconfig"
662 source "arch/arm/mach-lpc32xx/Kconfig"
664 source "arch/arm/mach-mediatek/Kconfig"
666 source "arch/arm/mach-meson/Kconfig"
668 source "arch/arm/mach-milbeaut/Kconfig"
670 source "arch/arm/mach-mmp/Kconfig"
672 source "arch/arm/mach-moxart/Kconfig"
674 source "arch/arm/mach-mstar/Kconfig"
676 source "arch/arm/mach-mv78xx0/Kconfig"
678 source "arch/arm/mach-mvebu/Kconfig"
680 source "arch/arm/mach-mxs/Kconfig"
682 source "arch/arm/mach-nomadik/Kconfig"
684 source "arch/arm/mach-npcm/Kconfig"
686 source "arch/arm/mach-nspire/Kconfig"
688 source "arch/arm/plat-omap/Kconfig"
690 source "arch/arm/mach-omap1/Kconfig"
692 source "arch/arm/mach-omap2/Kconfig"
694 source "arch/arm/mach-orion5x/Kconfig"
696 source "arch/arm/mach-oxnas/Kconfig"
698 source "arch/arm/mach-picoxcell/Kconfig"
700 source "arch/arm/mach-prima2/Kconfig"
702 source "arch/arm/mach-pxa/Kconfig"
703 source "arch/arm/plat-pxa/Kconfig"
705 source "arch/arm/mach-qcom/Kconfig"
707 source "arch/arm/mach-rda/Kconfig"
709 source "arch/arm/mach-realtek/Kconfig"
711 source "arch/arm/mach-realview/Kconfig"
713 source "arch/arm/mach-rockchip/Kconfig"
715 source "arch/arm/mach-s3c/Kconfig"
717 source "arch/arm/mach-s5pv210/Kconfig"
719 source "arch/arm/mach-sa1100/Kconfig"
721 source "arch/arm/mach-shmobile/Kconfig"
723 source "arch/arm/mach-socfpga/Kconfig"
725 source "arch/arm/mach-spear/Kconfig"
727 source "arch/arm/mach-sti/Kconfig"
729 source "arch/arm/mach-stm32/Kconfig"
731 source "arch/arm/mach-sunxi/Kconfig"
733 source "arch/arm/mach-tango/Kconfig"
735 source "arch/arm/mach-tegra/Kconfig"
737 source "arch/arm/mach-u300/Kconfig"
739 source "arch/arm/mach-uniphier/Kconfig"
741 source "arch/arm/mach-ux500/Kconfig"
743 source "arch/arm/mach-versatile/Kconfig"
745 source "arch/arm/mach-vexpress/Kconfig"
747 source "arch/arm/mach-vt8500/Kconfig"
749 source "arch/arm/mach-zx/Kconfig"
751 source "arch/arm/mach-zynq/Kconfig"
753 # ARMv7-M architecture
757 select GPIOLIB
765 select ARCH_HAS_RESET_CONTROLLER
766 select ARM_AMBA
767 select CLKSRC_LPC32XX
768 select PINCTRL
770 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
776 select ARM_AMBA
777 select CLKSRC_MPS2
779 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
780 with a range of available cores like Cortex-M3/M4/M7.
791 select GENERIC_CLOCKEVENTS
795 select CLKSRC_MMIO
796 select COMMON_CLK
797 select GENERIC_IRQ_CHIP
798 select IRQ_DOMAIN
802 select PLAT_ORION
821 source "arch/arm/Kconfig-nommu"
839 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
842 Executing a SWP instruction to read-only memory does not set bit 11
860 This option enables the workaround for the 430973 Cortex-A8
863 same virtual address, whether due to self-modifying code or virtual
864 to physical address re-mapping, Cortex-A8 does not recover from the
865 stale interworking branch prediction. This results in Cortex-A8
870 available in non-secure mode.
877 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
884 register may not be available in non-secure mode.
891 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
895 workaround disables the write-allocate mode for the L2 cache via the
897 may not be available in non-secure mode.
904 This option enables the workaround for the 742230 Cortex-A9
908 the diagnostic register of the Cortex-A9 which causes the DMB
917 This option enables the workaround for the 742231 Cortex-A9
919 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
924 register of the Cortex-A9 which reduces the linefill issuing
932 This option enables the workaround for the 643719 Cortex-A9 (prior to
942 This option enables the workaround for the 720789 Cortex-A9 (prior to
955 This option enables the workaround for the 743622 Cortex-A9
957 optimisation in the Cortex-A9 Store Buffer may lead to data
959 register of the Cortex-A9 which disables the Store Buffer
969 This option enables the workaround for the 751472 Cortex-A9 (prior
979 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
982 can populate the micro-TLB with a stale entry which may be hit with
990 This option enables the workaround for the 754327 Cortex-A9 (prior to
998 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1003 hit-under-miss enabled). It sets the undocumented bit 31 in
1005 register, thus disabling hit-under-miss without putting the
1014 affecting Cortex-A9 MPCore with two or more processors (all
1027 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1034 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1037 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1047 This option enables the workaround for the 773022 Cortex-A15
1057 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1059 - Cortex-A12 852422: Execution of a sequence of instructions might
1061 any Cortex-A12 cores yet.
1070 This option enables the workaround for the 821420 Cortex-A12
1074 deadlock when the VMOV instructions are issued out-of-order.
1080 This option enables the workaround for the 825619 Cortex-A12
1083 and Device/Strongly-Ordered loads and stores might cause deadlock
1089 This option enables the workaround for the 857271 Cortex-A12
1097 This option enables the workaround for the 852421 Cortex-A17
1107 - Cortex-A17 852423: Execution of a sequence of instructions might
1109 any Cortex-A17 cores yet.
1110 This is identical to Cortex-A12 erratum 852422. It is a separate
1111 config option from the A12 erratum due to the way errata are checked
1118 This option enables the workaround for the 857272 Cortex-A17 erratum.
1120 This is identical to Cortex-A12 erratum 857271. It is a separate
1121 config option from the A12 erratum due to the way errata are checked
1134 name of a bus system, i.e. the way the CPU talks to the other stuff
1139 # Select ISA DMA controller support
1142 select ISA_DMA_API
1144 # Select ISA DMA interface
1155 bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
1161 However, because of this erratum, an L2 set/way cache maintenance
1162 operation can overtake an L1 set/way cache maintenance operation.
1163 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
1173 This option should be selected by machines which have an SMP-
1176 The only effect of this option is to make the SMP-related
1180 bool "Symmetric Multi-Processing"
1185 select IRQ_WORK
1191 If you say N here, the kernel will run on uni- and multiprocessor
1197 See also <file:Documentation/x86/i386/IO-APIC.rst>,
1198 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
1199 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1208 SMP kernels contain instructions which fail on non-SMP processors.
1225 bool "Multi-core scheduler support"
1228 Multi-core scheduler support improves the CPU scheduler's decision
1229 making when dealing with multi-core CPU chips at a cost of slightly
1248 select ARM_ARCH_TIMER
1258 bool "Multi-Cluster Power Management"
1262 for (multi-)cluster based systems, such as big.LITTLE based
1271 Platforms with 3 or 4 clusters that use MCPM must select this
1277 select MCPM
1285 select CPU_PM
1304 Select the desired split between kernel and user memory.
1329 int "Maximum number of CPUs (2-32)"
1335 bool "Support for hot-pluggable CPUs"
1337 select GENERIC_IRQ_MIGRATION
1345 select ARM_PSCI_FW
1348 implementing the PSCI specification for CPU-centric power
1418 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1421 select ARM_UNWIND
1424 Thumb-2 mode.
1475 selected, since there is no way yet to sensibly distinguish
1492 select SPARSEMEM_STATIC if SPARSEMEM
1515 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1523 user-space 2nd level page tables to reside in high memory.
1526 bool "Enable use of CPU domains to implement privileged no-access"
1532 use-after-free bugs becoming an exploitable privilege escalation
1536 CPUs with low-vector mappings use a best-efforts implementation.
1569 Disabling this is usually safe for small single-platform
1592 select HAVE_PROC_CPU if PROC_FS
1596 address divisible by 4. On 32-bit ARM processors, these non-aligned
1599 correct operation of some network protocols. With an IP-only
1608 cores where a 8-word STM instruction give significantly higher
1615 However, if the CPU data cache is using a write-allocate mode,
1627 select PARAVIRT
1629 Select this option to enable fine granularity task steal time
1646 select ARCH_DMA_ADDR_T_64BIT
1647 select ARM_PSCI
1648 select SWIOTLB
1649 select SWIOTLB_XEN
1650 select PARAVIRT
1657 select GCC_PLUGIN_ARM_SSP_PER_TASK
1675 select IRQ_DOMAIN
1676 select OF
1684 This is the traditional way of passing data to the kernel at boot
1691 bool "Provide old way to pass kernel parameters"
1695 Some old boot loaders still use this way.
1703 The physical address at which the ROM-able zImage is to be
1705 ROM-able zImage formats normally set this to a suitable
1715 for the ROM-able zImage which must be available while the
1718 Platforms which normally make use of ROM-able zImage formats
1770 Uses the command-line options passed by the boot loader instead of
1777 The command-line arguments provided by the boot loader will be
1786 On some architectures (EBSA110 and CATS), there is currently no way
1788 architectures, you should supply some command-line options at build
1799 Uses the command-line options passed by the boot loader. If
1806 The command-line arguments provided by the boot loader will be
1815 command-line options your boot loader passes to the kernel.
1819 bool "Kernel Execute-In-Place from ROM"
1822 Execute-In-Place allows the kernel to run from non-volatile storage
1825 to RAM. Read-write sections, such as the data section and stack,
1851 select ZLIB_INFLATE
1863 select KEXEC_CORE
1887 loaded in the main kernel with kexec-tools into a specially
1892 For more details see Documentation/admin-guide/kdump/kdump.rst
1899 will be determined at run-time by masking the current IP with
1909 select UCS2_STRING
1910 select EFI_PARAMS_FROM_FDT
1911 select EFI_STUB
1912 select EFI_GENERIC_STUB
1913 select EFI_RUNTIME_WRAPPERS
1916 by UEFI firmware (such as non-volatile variables, realtime
1931 continue to boot on existing non-UEFI platforms.
1937 to be enabled much earlier than we do on ARM, which is non-trivial.
1960 your machine has an FPA or floating point co-processor podule.
1969 Say Y to include 80-bit support in the kernel floating-point
1970 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1971 Note that gcc does not generate 80-bit operations by default,
1984 It is very simple, and approximately 3-6 times faster than NWFPE.
1992 bool "VFP-format floating point maths"
1998 Please see <file:Documentation/arm/vfp/release-notes.rst> for