281 		write_aux_reg(aux_cmd, paddr);  in __cache_line_loop_v2()
327 		write_aux_reg(aux_tag, paddr);  in __cache_line_loop_v3()
337 		write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32);  in __cache_line_loop_v3()
341 			write_aux_reg(aux_tag, paddr);  in __cache_line_loop_v3()
345 		write_aux_reg(aux_cmd, vaddr);  in __cache_line_loop_v3()
403 			write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32);  in __cache_line_loop_v4()
405 			write_aux_reg(ARC_REG_DC_PTAG_HI, (u64)paddr >> 32);  in __cache_line_loop_v4()
409 		write_aux_reg(aux_cmd, paddr);  in __cache_line_loop_v4()
449 			write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32);  in __cache_line_loop_v4()
451 			write_aux_reg(ARC_REG_DC_PTAG_HI, (u64)paddr >> 32);  in __cache_line_loop_v4()
455 	write_aux_reg(e, paddr + sz);	/* ENDR is exclusive */  in __cache_line_loop_v4()
456 	write_aux_reg(s, paddr);  in __cache_line_loop_v4()
491 		write_aux_reg(ctl, read_aux_reg(ctl) | DC_CTRL_INV_MODE_FLUSH);  in __before_dc_op()
515 	write_aux_reg(ctl, val);  in __before_dc_op()
533 			write_aux_reg(ctl, reg & ~DC_CTRL_INV_MODE_FLUSH);  in __after_dc_op()
554 	write_aux_reg(aux, 0x1);  in __dc_entire_op()
564 	write_aux_reg(r, read_aux_reg(r) | DC_CTRL_DIS);  in __dc_disable()
571 	write_aux_reg(r, read_aux_reg(r) & ~DC_CTRL_DIS);  in __dc_enable()
611 	write_aux_reg(ARC_REG_IC_IVIC, 1);  in __ic_entire_inv()
702 	write_aux_reg(ARC_REG_SLC_CTRL, ctrl);  in slc_op_rgn()
711 		write_aux_reg(ARC_REG_SLC_RGN_END1, upper_32_bits(end));  in slc_op_rgn()
713 	write_aux_reg(ARC_REG_SLC_RGN_END, lower_32_bits(end));  in slc_op_rgn()
716 		write_aux_reg(ARC_REG_SLC_RGN_START1, upper_32_bits(paddr));  in slc_op_rgn()
718 	write_aux_reg(ARC_REG_SLC_RGN_START, lower_32_bits(paddr));  in slc_op_rgn()
756 	write_aux_reg(ARC_REG_SLC_CTRL, ctrl);  in slc_op_line()
766 		write_aux_reg(cmd, paddr);  in slc_op_line()
792 	write_aux_reg(r, ctrl);  in slc_entire_op()
795 		write_aux_reg(ARC_REG_SLC_INVALIDATE, 0x1);  in slc_entire_op()
797 		write_aux_reg(ARC_REG_SLC_FLUSH, 0x1);  in slc_entire_op()
811 	write_aux_reg(r, read_aux_reg(r) | SLC_CTRL_DIS);  in arc_slc_disable()
818 	write_aux_reg(r, read_aux_reg(r) & ~SLC_CTRL_DIS);  in arc_slc_enable()
1193 	write_aux_reg(ARC_REG_IO_COH_AP0_SIZE, order_base_2(mem_sz >> 10) - 2);  in arc_ioc_setup()
1201 	write_aux_reg(ARC_REG_IO_COH_AP0_BASE, ioc_base >> 12);  in arc_ioc_setup()
1202 	write_aux_reg(ARC_REG_IO_COH_PARTIAL, ARC_IO_COH_PARTIAL_BIT);  in arc_ioc_setup()
1203 	write_aux_reg(ARC_REG_IO_COH_ENABLE, ARC_IO_COH_ENABLE_BIT);  in arc_ioc_setup()
1320 			write_aux_reg(ARC_REG_IC_PTAG_HI, 0);  in arc_cache_init()
1323 			write_aux_reg(ARC_REG_DC_PTAG_HI, 0);  in arc_cache_init()
1326 			write_aux_reg(ARC_REG_SLC_RGN_END1, 0);  in arc_cache_init()
1327 			write_aux_reg(ARC_REG_SLC_RGN_START1, 0);  in arc_cache_init()