491 		write_aux_reg(ctl, read_aux_reg(ctl) | DC_CTRL_INV_MODE_FLUSH);  in __before_dc_op()
500 	unsigned int val = read_aux_reg(ctl);  in __before_dc_op()
528 		while ((reg = read_aux_reg(ctl)) & DC_CTRL_FLUSH_STATUS)  in __after_dc_op()
564 	write_aux_reg(r, read_aux_reg(r) | DC_CTRL_DIS);  in __dc_disable()
571 	write_aux_reg(r, read_aux_reg(r) & ~DC_CTRL_DIS);  in __dc_enable()
612 	read_aux_reg(ARC_REG_IC_CTRL);	/* blocks */  in __ic_entire_inv()
689 	ctrl = read_aux_reg(ARC_REG_SLC_CTRL);  in slc_op_rgn()
721 	read_aux_reg(ARC_REG_SLC_CTRL);  in slc_op_rgn()
723 	while (read_aux_reg(ARC_REG_SLC_CTRL) & SLC_CTRL_BUSY);  in slc_op_rgn()
748 	ctrl = read_aux_reg(ARC_REG_SLC_CTRL);  in slc_op_line()
771 	read_aux_reg(ARC_REG_SLC_CTRL);  in slc_op_line()
773 	while (read_aux_reg(ARC_REG_SLC_CTRL) & SLC_CTRL_BUSY);  in slc_op_line()
785 	ctrl = read_aux_reg(r);  in slc_entire_op()
800 	read_aux_reg(r);  in slc_entire_op()
803 	while (read_aux_reg(r) & SLC_CTRL_BUSY);  in slc_entire_op()
811 	write_aux_reg(r, read_aux_reg(r) | SLC_CTRL_DIS);  in arc_slc_disable()
818 	write_aux_reg(r, read_aux_reg(r) & ~SLC_CTRL_DIS);  in arc_slc_enable()
1166 	if (read_aux_reg(ARC_REG_IO_COH_ENABLE) & ARC_IO_COH_ENABLE_BIT)  in arc_ioc_setup()
1176 	if (read_aux_reg(ARC_REG_SLC_BCR))  in arc_ioc_setup()