Lines Matching +full:dsp +full:- +full:reset
1 # SPDX-License-Identifier: GPL-2.0-only
3 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
98 source "arch/arc/plat-tb10x/Kconfig"
99 source "arch/arc/plat-axs10x/Kconfig"
100 source "arch/arc/plat-hsdk/Kconfig"
118 ISA for the Next Generation ARC-HS cores
143 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
145 -Caches: New Prog Model, Region Flush
146 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
151 bool "ARC-HS"
156 - SMP configurations of up to 4 cores with coherency
157 - Optional L2 Cache and IO-Coherency
158 - Revised Interrupt Architecture (multiple priorites, reg banks,
160 - MMUv4 (PIPT dcache, Huge Pages)
161 - Instructions for
172 string "Override default -mcpu compiler flag"
175 Override default -mcpu=xxx compiler flag (which is set depending on
186 bool "Symmetric Multi-Processing"
194 int "Maximum number of CPUs (2-4096)"
199 bool "Enable Halt-on-reset boot mode"
201 In SMP configuration cores can be configured as Halt-on-reset
202 or they could all start at same time. For Halt-on-reset, non
214 This IP block enables SMP in ARC-HS38 cores.
215 It provides for cross-core interrupts, multi-core debug
230 This option specifies "N", with Line-len = 2 power N
247 This can be used to over-ride the global I/D Cache Enable on a
248 per-page basis (but only for pages accessed via MMU such as
250 TLB entries have a per-page Cache Enable Bit.
301 Fixed the deficiency of v1 - possible thrashing in memcpy scenario
302 when 2 D-TLB and 1 I-TLB entries index into same 2way set.
309 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
365 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
385 bool "Insn: SWAPE (endian-swap)"
402 Enable gcc to generate 64-bit load/store instructions
412 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6 and/or DSP)"
415 Depending on the configuration, CPU can contain accumulator reg-pair
426 prompt "DSP support"
429 Depending on the configuration, CPU can contain DSP registers
435 bool "No DSP extension presence in HW"
437 No DSP extension presence in HW
440 bool "DSP extension in HW, no support for userspace"
444 DSP extension presence in HW, no support for DSP-enabled userspace
445 applications. We don't save / restore DSP registers and only do
449 bool "Support DSP for userspace apps"
454 DSP extension presence in HW, support save / restore DSP registers to
455 run DSP-enabled userspace applications
458 bool "Support DSP with AGU for userspace apps"
463 DSP and AGU extensions presence in HW, support save / restore DSP
464 and AGU registers to run DSP-enabled userspace applications
490 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
491 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
516 bool "Support for the 40-bit Physical Address Extension"
533 kernel-user gutter)
550 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
562 Metaware Debugger. This can come in handy for Linux-host communication
592 Enable paranoid checks and self-test of both ARC-specific and generic