Documentation/x86/sva.rst

1 .. SPDX-License-Identifier: GPL-2.0
19 application page-faults. For more information please refer to the PCIe
28 CPU page tables. The device must use ATS again in order the fetch the
34 Unlike Single Root I/O Virtualization (SR-IOV), Scalable IOV (SIOV) permits
40 ID (PASID), which is a 20-bit number defined by the PCIe SIG.
43 IOMMU to track I/O on a per-PASID granularity in addition to using the PCIe
55 ENQCMD works with non-posted semantics and carries a status back if the
67 A new thread-scoped MSR (IA32_PASID) provides the connection between
69 accesses an SVA-capable device, this MSR is initialized with a newly
70 allocated PASID. The driver for the device calls an IOMMU-specific API
71 that sets up the routing for DMA and page-requests.
76 - Allocate the PASID, and program the process page-table (%cr3 register) in the
78 - Register for mmu_notifier() to track any page-table invalidations to keep
79   the device TLB in sync. For example, when a page-table entry is invalidated,
96 ENQCMD instruction, the PASID field in the descriptor is auto-filled with the
134  * The single process-wide PASID is used by all threads to interact
136    thread or each thread<->device pair.
151 A Process Address Space ID (PASID) is a PCIe-defined Transaction Layer Packet
152 (TLP) prefix. A PASID is a 20-bit number allocated and managed by the OS.
160 Each doorbell is required to be spaced 4k (or page-size) apart for process
163 hardware also manages the queue depth for Shared Work Queues (SWQ), and
164 consumers don't need to track queue depth. If there is no space to accept
186 * Is this the same as SR-IOV?
188 Single Root I/O Virtualization (SR-IOV) focuses on providing independent
191 BARs, space for interrupts via MSI-X, its own register layout.
200 demand. SR-IOV creation and management is very static in nature. Consult
205 Creating PCIe SR-IOV type Virtual Functions (VF) is expensive. VFs require
206 duplicated hardware for PCI config space and interrupts such as MSI-X.
211 creates a software-defined device where all the configuration and control
229 Device TLB support - Device requests the IOMMU to lookup an address before
239 IOMMU works with the OS in managing consistency of page-tables with the
247 VT-D:
248 https://01.org/blogs/ashokraj/2018/recent-enhancements-intel-virtualization-technology-directed-i/o…
251 https://01.org/blogs/2019/assignable-interfaces-intel-scalable-i/o-virtualization-linux
254 …intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-re…
257 https://software.intel.com/sites/default/files/341204-intel-data-streaming-accelerator-spec.pdf