Documentation/sparc/adi.rst

19 2. Set TTE.mcd bit on any TLB entries that correspond to the range of
24    and one of the MCD specific ASIs. Each stxa instruction sets the
34 SPARC M7 processor, MMU uses bits 63-60 for version tags and ADI block
35 size is same as cacheline size which is 64 bytes. A task that sets ADI
37 virtual addresses that contain 0xa in bits 63-60.
41 kernel sets the PSTATE.mcde bit fot the task. Version tags for memory
58 - Version tag values of 0x0 and 0xf are reserved. These values match any
61 - Version tags are set on virtual addresses from userspace even though
66 - When a task frees a memory page it had set version tags on, the page
67   goes back to free page pool. When this page is re-allocated to a task,
73 - ADI tag mismatches are not detected for non-faulting loads.
75 - Kernel does not set any tags for user pages and it is entirely a
81 - ADI works for any size pages. A userspace task need not be aware of
87 - ADI tags can only be set on writable memory. For example, ADI tags can
88   not be set on read-only mappings.
98 ----------------------------
118 -------------------------
140 ------------
157 -------------------------
186           unsigned long i, mcde, adi_blksz, adi_nbits;
194 	for (auxv = (Elf64_auxv_t *)envp; auxv->a_type != AT_NULL; auxv++) {
195 		switch (auxv->a_type) {
197 			adi_blksz = auxv->a_un.a_val;
200 			adi_nbits = auxv->a_un.a_val;
220           if (shmaddr == (char *)-1) {
250           veraddr = (void *) (((unsigned long)version << (64-adi_nbits))
254           for (i = 0; i < BUFFER_SIZE; i++) {
255                   veraddr[i] = (char)(i);
256                   if (!(i % (1024 * 1024)))
263           for (i = 0; i < BUFFER_SIZE; i++)
264                   if (veraddr[i] != (char)i)
265                           printf("\nIndex %lu mismatched\n", i);