Lines Matching full:tcs
6 can be written to the Trigger Command Set (TCS) registers and using a (addr,
7 val) pair and triggered. Messages in the TCS are then sent in sequence over an
16 A TCS may be triggered from Linux or triggered by the F/W after all the CPUs
17 have powered off to facilitate idle power saving. TCS could be classified as -
45 The tcs-offset specifies the start address of the
46 TCS in the DRVs.
52 "drv-0", "drv-1", "drv-2" etc and "tcs-offset". The
66 - qcom,tcs-config:
69 Definition: The tuple defining the configuration of TCS.
70 Must have 2 cells which describe each TCS type.
72 The order of the TCS must match the hardware
74 - Cell #1 (TCS Type): TCS types to be specified -
79 - Cell #2 (Number of TCS): <u32>
91 For a TCS whose RSC base address is is 0x179C0000 and is at a DRV id of 2, the
97 TCS-OFFSET: 0xD00
109 qcom,tcs-offset = <0xd00>;
111 qcom,tcs-config = <ACTIVE_TCS 2>,
119 For a TCS whose RSC base address is 0xAF20000 and is at DRV id of 0, the
123 TCS-OFFSET: 0x1C00
131 qcom,tcs-offset = <0x1c00>;
133 qcom,tcs-config = <ACTIVE_TCS 0>,