Lines Matching +full:assigned +full:- +full:clocks
5 - compatible : should be one of the following.
6 "rockchip,cryptov1-rng" for crypto v1
7 "rockchip,cryptov2-rng" for crypto v2
9 - reg : Specifies base physical address and size of the registers map.
10 - clocks : Phandle to clock-controller plus clock-specifier pair.
11 - clock-names : "clk_crypto", "clk_crypto_apk", "aclk_crypto", "hclk_crypto" as a clock name.
12 - assigned-clocks: Main clock, should be <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>,
14 - assigned-clock-rates : The rng core clk frequency, shall be: <150000000>, <150000000>,
16 - resets : Used for module reset
17 - reset-names : Reset names, should be "reset"
21 compatible = "rockchip,cryptov1-rng";
23 clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO>;
24 clock-names = "clk_crypto", "hclk_crypto";
25 assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO>;
26 assigned-clock-rates = <150000000>, <100000000>;
28 reset-names = "reset";
33 compatible = "rockchip,cryptov2-rng";
35 clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>,
37 clock-names = "clk_crypto", "clk_crypto_apk",
39 assigned-clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>,
41 assigned-clock-rates = <150000000>, <150000000>,
44 reset-names = "reset";