bindings/pinctrl/fsl%2Cimx7d-pinctrl.txt

4 as previous iMX SoC generation and fsl,imx7d-iomuxc-lpsr which provides low
5 power state retention capabilities on gpios that are part of iomuxc-lpsr
6 (GPIO1_IO7..GPIO1_IO0). While iomuxc-lpsr provides its own set of registers for
9 fsl,imx-pinctrl driver to support iomuxc-lpsr controller.
11 iomuxc_lpsr: iomuxc-lpsr@302c0000 {
12 	compatible = "fsl,imx7d-iomuxc-lpsr";
22 Peripherals using pads from iomuxc-lpsr support low state retention power
23 state, under LPSR mode GPIO's state of pads are retain.
30   "fsl,imx7d-iomuxc-lpsr" for Low Power State Retention IOMUXC controller.
37 - fsl,input-sel: required property for iomuxc-lpsr controller, this property is
56 While iomuxc-lpsr is intended to be used by dedicated peripherals to take
57 advantages of LPSR power mode, is also possible that an IP to use pads from
59 iomuxc-lpsr controller and SDA pad from iomuxc controller as:
66 iomuxc-lpsr@302c0000 {
67 	compatible = "fsl,imx7d-iomuxc-lpsr";