bindings/phy/samsung-phy.txt

14 In case of exynos5433 compatible PHY:
21 the PHY specifier identifies the PHY and its meaning is as follows:
27 supports additional fifth PHY:
30 Samsung Exynos SoC series Display Port PHY
39 - #phy-cells : from the generic PHY bindings, must be 0;
41 Samsung S5P/Exynos SoC series USB PHY
59 	  PHY module
64 The first phandle argument in the PHY specifier identifies the PHY, its
90 Then the PHY can be used in other nodes such as:
97 Refer to DT bindings documentation of particular PHY consumer devices for more
100 Samsung SATA PHY Controller
103 SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
104 Each SATA PHY controller should have its own node.
108 - reg : offset and length of the SATA PHY register set;
140 Samsung Exynos5 SoC series USB DRD PHY controller
149 - reg : Register offset and length of USB DRD PHY register set;
153 	- phy: main PHY clock (same as USB DRD controller i.e. DWC3 IP clock),
155 	- ref: PHY's reference clock (usually crystal clock), used for
156 	       PHY operations, associated by phy name. It is used to
166 - #phy-cells : from the generic PHY bindings, must be 1;
169 compatible PHYs, the second cell in the PHY specifier identifies the
170 PHY id, which is interpreted as follows:
184 - aliases: For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers,
194 Samsung Exynos SoC series PCIe PHY controller