bindings/phy/samsung%2Cufs-phy.yaml

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Alim Akhtar <alim.akhtar@samsung.com>
13   "#phy-cells":
18       - samsung,exynos7-ufs-phy
23   reg-names:
25       - const: phy-pma
29       - description: PLL reference clock
30       - description: symbol clock for input symbol ( rx0-ch0 symbol clock)
31       - description: symbol clock for input symbol ( rx1-ch1 symbol clock)
32       - description: symbol clock for output symbol ( tx0 symbol clock)
34   clock-names:
36       - const: ref_clk
37       - const: rx1_symbol_clk
38       - const: rx0_symbol_clk
39       - const: tx0_symbol_clk
41   samsung,pmu-syscon:
43     description: phandle for PMU system controller interface, used to
44                  control pmu registers bits for ufs m-phy
47   - "#phy-cells"
48   - compatible
49   - reg
50   - reg-names
51   - clocks
52   - clock-names
53   - samsung,pmu-syscon
58   - |
59     #include <dt-bindings/clock/exynos7-clk.h>
61     ufs_phy: ufs-phy@15571800 {
62         compatible = "samsung,exynos7-ufs-phy";
64         reg-names = "phy-pma";
65         samsung,pmu-syscon = <&pmu_system_controller>;
66         #phy-cells = <0>;
71         clock-names = "ref_clk", "rx1_symbol_clk",