bindings/phy/phy-rockchip-usbdp.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-usbdp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Frank Wang <frank.wang@rock-chips.com>
11   - Zhang Yubing <yubing.zhang@rock-chips.com>
16       - rockchip,rk3588-usbdp-phy
23       - description: phy ref clock.
24       - description: phy pcs immortal clock.
25       - description: phy peripheral clock.
27   clock-names:
29       - const: refclk
30       - const: immortal
31       - const: pclk
34       - description: phy init reset.
35       - description: phy cmn reset.
36       - description: phy lane reset.
37       - description: phy pcs apb reset.
38       - description: phy pma apb reset.
40   reset-names:
41       - const: init
42       - const: cmn
43       - const: lane
44       - const: pcs_apb
45       - const: pma_apb
47   rockchip,dp-lane-mux:
51       An array of physical Tyep-C lanes indexes. Position of an entry determines
52       the dp lane index, while the value of an entry indicater physical Type-C lane.
54       have "rockchip,dp-lane-mux = <2, 3>;", assuming dp lane0 on Type-C phy lane2,
55       dp lane1 on Type-C phy lane3. For 4 lanes dp lanes map, we could have
56       "rockchip,dp-lane-mux = <0, 1, 2, 3>;", assuming dp lane0 on Type-C phy lane0,
57       dp lane1 on Type-C phy lane1, dp lane2 on Type-C phy lane2, dp lane3 on Type-C
60   rockchip,u2phy-grf:
65   rockchip,usb-grf:
70   rockchip,usbdpphy-grf:
75   rockchip,vo-grf:
81   dp-port:
86       "#phy-cells":
90       - "#phy-cells"
92   u3-port:
97       "#phy-cells":
101       - "#phy-cells"
104   - compatible
105   - reg
106   - clocks
107   - clock-names
108   - resets
109   - reset-names
110   - dp-port
111   - u3-port
116   - |
117     #include <dt-bindings/clock/rk3588-cru.h>
120       compatible = "rockchip,rk3588-usbdp-phy";
122       rockchip,u2phy-grf = <&usb2phy0_grf>;
123       rockchip,usb-grf = <&usb_grf>;
124       rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
125       rockchip,vo-grf = <&vo0_grf>;
129       clock-names = "refclk", "immortal", "pclk";
135       reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
138       usbdp_phy0_dp: dp-port {
139         #phy-cells = <0>;
143       usbdp_phy0_u3: u3-port {
144         #phy-cells = <0>;