bindings/phy/phy-mtk-tphy.txt

1 MediaTek T-PHY binding
2 --------------------------
4 T-phy controller supports physical layer functionality for a number of
8  - compatible	: should be one of
9 		  "mediatek,generic-tphy-v1"
10 		  "mediatek,generic-tphy-v2"
11 		  "mediatek,mt2701-u3phy" (deprecated)
12 		  "mediatek,mt2712-u3phy" (deprecated)
13 		  "mediatek,mt8173-u3phy";
14 		  make use of "mediatek,generic-tphy-v1" on mt2701 instead and
15 		  "mediatek,generic-tphy-v2" on mt2712 instead.
17 - #address-cells:	the number of cells used to represent physical
19 - #size-cells:	the number of cells used to represent the size of an address.
20 - ranges:	the address mapping relationship to the parent, defined with
21 		- empty value: if optional 'reg' is used.
22 		- non-empty value: if optional 'reg' is not used. should set
27 Required nodes	: a sub-node is required for each port the controller
33  - reg		: offset and length of register shared by multiple ports,
34 		  exclude port's private register. It is needed on mt2701
36  - mediatek,src-ref-clk-mhz	: frequency of reference clock for slew rate
38  - mediatek,src-coef	: coefficient for slew rate calibrate, depends on
41 Required properties (port (child) node):
42 - reg		: address and length of the register set for the port.
43 - #phy-cells	: should be 1 (See second example)
44 		  cell after port phandle is phy type from:
45 			- PHY_TYPE_USB2
46 			- PHY_TYPE_USB3
47 			- PHY_TYPE_PCIE
48 			- PHY_TYPE_SATA
50 Optional properties (PHY_TYPE_USB2 port (child) node):
51 - clocks	: a list of phandle + clock-specifier pairs, one for each
52 		  entry in clock-names
53 - clock-names	: may contain
61 - mediatek,eye-src	: u32, the value of slew rate calibrate
62 - mediatek,eye-vrt	: u32, the selection of VRT reference voltage
63 - mediatek,eye-term	: u32, the selection of HS_TX TERM reference voltage
64 - mediatek,bc12	: bool, enable BC12 of u2phy if support it
65 - mediatek,discth	: u32, the selection of disconnect threshold
66 - mediatek,intr	: u32, the selection of internal R (resistance)
70 u3phy: usb-phy@11290000 {
71 	compatible = "mediatek,mt8173-u3phy";
73 	#address-cells = <2>;
74 	#size-cells = <2>;
77 	u2port0: usb-phy@11290800 {
80 		clock-names = "ref";
81 		#phy-cells = <1>;
84 	u3port0: usb-phy@11290900 {
87 		clock-names = "ref";
88 		#phy-cells = <1>;
91 	u2port1: usb-phy@11291000 {
94 		clock-names = "ref";
95 		#phy-cells = <1>;
100 ---------------------------------
103 property, containing a phandle to the phy port node and a device type;
104 phy-names for each port are optional.
108 #include <dt-bindings/phy/phy.h>
113 	phy-names = "usb2-0", "usb3-0";
119 -------------------------------------------------------------
121 port        offset    bank
125 u3 port0    0x0900    U3PHYD
130 u3 port1    0x1100    U3PHYD
138 port        offset    bank
142 u3 port0    0x0700    SPLLC
151 u3 port1    0x1700    SPLLC
160     SPLLC shared by u3 ports and FMREG shared by u2 ports on
161 mt8173/mt2701 are put back into each port; a new bank MISC for
162 u2 ports and CHIP for u3 ports are added on mt2712.