Lines Matching full:lanes

4 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
7 documentation. Each such "pad" may control either one or multiple lanes,
8 and thus contains any logic common to all its lanes. Each lane can be
11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
15 ports (e.g. PCIe) and the lanes.
80 the pad and any of its lanes, this property must be set to "okay".
127 Each pad node has a child named "lanes" that contains one or more children of
128 its own, each representing one of the lanes controlled by the pad.
283 				lanes {
304 				lanes {
315 				lanes {
331 				lanes {
362 				lanes {
415 				lanes {
436 				lanes {
457 				lanes {
513 				lanes {
541 				lanes {
561 				lanes {
606 				lanes {
667 				lanes {
693 				lanes {
734 				lanes {
768 				nvidia,lanes = "pcie-6";
774 				nvidia,lanes = "pcie-5";