bindings/phy/intel%2Ccombo-phy.yaml

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/intel,combo-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel ComboPhy Subsystem
10   - Dilip Kota <eswara.kota@linux.intel.com>
13   Intel Combophy subsystem supports PHYs for PCIe, EMAC and SATA
14   controllers. A single Combophy provides two PHY instances.
18     pattern: "combophy(@.*|-[0-9a-f])*$"
22       - const: intel,combophy-lgm
23       - const: intel,combo-phy
30       - description: ComboPhy core registers
31       - description: PCIe app core control registers
33   reg-names:
35       - const: core
36       - const: app
41   reset-names:
43       - const: phy
44       - const: core
45       - const: iphy0
46       - const: iphy1
49     $ref: /schemas/types.yaml#/definitions/phandle-array
50     description: Chip configuration registers handle and ComboPhy instance id
53     $ref: /schemas/types.yaml#/definitions/phandle-array
54     description: HSIO registers handle and ComboPhy instance id on NOC
59       Specify the flag to configure ComboPHY in dual lane mode.
61   intel,phy-mode:
64       Mode of the two phys in ComboPhy.
65       See dt-bindings/phy/phy.h for values.
67   "#phy-cells":
71   - compatible
72   - clocks
73   - reg
74   - reg-names
75   - intel,syscfg
76   - intel,hsio
77   - intel,phy-mode
78   - "#phy-cells"
83   - |
84     #include <dt-bindings/phy/phy.h>
85     combophy@d0a00000 {
86         compatible = "intel,combophy-lgm", "intel,combo-phy";
88         #phy-cells = <1>;
91         reg-names = "core", "app";
96         reset-names = "phy", "core", "iphy0", "iphy1";
99         intel,phy-mode = <PHY_TYPE_PCIE>;