bindings/pci/layerscape-pci.txt

1 Freescale Layerscape PCIe controller
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4 and thus inherits all the common properties defined in designware-pcie.txt.
7 which is used to describe the PLL settings at the time of chip-reset.
10 register available in the Freescale PCIe controller register set,
11 which can allow determining the underlying DesignWare PCIe controller version
15 - compatible: should contain the platform identifier such as:
17         "fsl,ls1021a-pcie"
18         "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
19         "fsl,ls2088a-pcie"
20         "fsl,ls1088a-pcie"
21         "fsl,ls1046a-pcie"
22         "fsl,ls1043a-pcie"
23         "fsl,ls1012a-pcie"
24         "fsl,ls1028a-pcie"
26 	"fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"
27 	"fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"
28 	"fsl,ls2088a-pcie-ep", "fsl,ls-pcie-ep"
29 - reg: base addresses and lengths of the PCIe controller register blocks.
30 - interrupts: A list of interrupt outputs of the controller. Must contain an
31   entry for each entry in the interrupt-names property.
32 - interrupt-names: Must include the following entries:
34 - fsl,pcie-scfg: Must include two entries.
36   The second entry must be '0' or '1' based on physical PCIe controller index.
38 - dma-coherent: Indicates that the hardware IP block can ensure the coherency
44 	pcie@3400000 {
45 		compatible = "fsl,ls1021a-pcie";
48 		reg-names = "regs", "config";
50 		interrupt-names = "intr";
51 		fsl,pcie-scfg = <&scfg 0>;
52 		#address-cells = <3>;
53 		#size-cells = <2>;
55 		dma-coherent;
56 		num-lanes = <4>;
57 		bus-range = <0x0 0xff>;
60 			  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
61 		#interrupt-cells = <1>;
62 		interrupt-map-mask = <0 0 0 7>;
63 		interrupt-map = <0000 0 0 1 &gic GIC_SPI 91  IRQ_TYPE_LEVEL_HIGH>,