Lines Matching refs:Port

34 - reg: Port address described must be 6 for CPU port and from 0 to 5 for
43 Port 5 of mt7530 and mt7621 switch is muxed between:
51 Port 5 modes/configurations:
52 1. Port 5 is disabled and isolated: An external phy can interface to the 2nd
56 2. Port 5 is muxed to PHY of port 0/4: Port 0/4 interfaces with 2nd GMAC.
59 3. Port 5 is muxed to GMAC5 and can interface to an external phy.
60    Port 5 becomes an extra switch port.
63 4. Port 5 is muxed to GMAC5 and interfaces with the 2nd GAMC as 2nd CPU port.
139 Example 2: MT7621: Port 4 is WAN port: 2nd GMAC -> Port 5 -> PHY port 4.
205 /* Commented out. Port 4 is handled by 2nd GMAC.
229 Example 3: MT7621: Port 5 is connected to external PHY: Port 5 -> external PHY.