Lines Matching full:sdhc

6 Each SDHC is independent and owns independent resources, such as register sets,
8 Each SDHC should have an independent device tree node.
18   Array of clocks required for SDHC.
38 - marvell,xenon-sdhc-id:
39   Indicate the corresponding bit index of current SDHC in
40   SDHC System Operation Control Register Bit[7:0].
41   Set/clear the corresponding bit to enable/disable current SDHC.
42   If Xenon IP contains only one SDHC, this property is optional.
54   It doesn't stand for the entire SDHC type or property.
55   For example, "emmc 5.1 phy" doesn't mean that this Xenon SDHC only
88   Xenon SDHC SoC usually doesn't provide re-tuning counter in