Lines Matching full:usdhc

30           - fsl,imx6q-usdhc
31           - fsl,imx6sl-usdhc
32           - fsl,imx6sx-usdhc
33           - fsl,imx6ull-usdhc
34           - fsl,imx7d-usdhc
35           - fsl,imx7ulp-usdhc
38               - fsl,imx8mm-usdhc
39               - fsl,imx8mn-usdhc
40               - fsl,imx8mp-usdhc
41               - fsl,imx8mq-usdhc
42               - fsl,imx8qxp-usdhc
43           - const: fsl,imx7d-usdhc
62       due to signal path is too long on the board. Please refer to eSDHC/uSDHC
89       The uSDHC use one delay cell as default increasing step to do tuning process.