Lines Matching full:emc
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
15 The EMC interfaces with the off-chip SDRAM to service the request stream
16 sent from Memory Controller. The EMC also has various performance-affecting
18 settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2,
23 const: nvidia,tegra30-emc
40 "^emc-timings-[0-9]+$":
58 nvidia,emc-auto-cal-interval:
65 nvidia,emc-mode-1:
70 nvidia,emc-mode-2:
75 nvidia,emc-mode-reset:
80 nvidia,emc-zcal-cnt-long:
82 Number of EMC clocks to wait before issuing any commands after
88 nvidia,emc-cfg-dyn-self-ref:
93 nvidia,emc-cfg-periodic-qrst:
98 nvidia,emc-configuration:
100 EMC timing characterization data. These are the registers
101 (see section "18.13.2 EMC Registers" in the TRM) whose values
197 - nvidia,emc-auto-cal-interval
198 - nvidia,emc-mode-1
199 - nvidia,emc-mode-2
200 - nvidia,emc-mode-reset
201 - nvidia,emc-zcal-cnt-long
202 - nvidia,emc-configuration
223 compatible = "nvidia,tegra30-emc";
230 emc-timings-1 {
236 nvidia,emc-auto-cal-interval = <0x001fffff>;
237 nvidia,emc-mode-1 = <0x80100002>;
238 nvidia,emc-mode-2 = <0x80200018>;
239 nvidia,emc-mode-reset = <0x80000b71>;
240 nvidia,emc-zcal-cnt-long = <0x00000040>;
241 nvidia,emc-cfg-periodic-qrst;
243 nvidia,emc-configuration = <