Lines Matching full:smmu
4 $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
18 The SMMU may also raise interrupts in response to various fault
26 - description: Qcom SoCs implementing "arm,smmu-v2"
29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2
31 - const: qcom,smmu-v2
36 - qcom,sc7180-smmu-500
37 - qcom,sdm845-smmu-500
38 - qcom,sm8150-smmu-500
39 - qcom,sm8250-smmu-500
41 - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
44 - qcom,sc7180-smmu-v2
45 - qcom,sdm845-smmu-v2
46 - const: qcom,adreno-smmu
47 - const: qcom,smmu-v2
50 - const: marvell,ap806-smmu-500
55 - nvidia,tegra194-smmu
56 - const: nvidia,smmu-500
59 - const: arm,smmu-v2
64 - const: arm,smmu-v1
66 - arm,smmu-v1
67 - arm,smmu-v2
71 - cavium,smmu-v2
88 by that device into the relevant SMMU.
101 interrupts, specified in order of their indexing by the SMMU.
109 Present if page table walks made by the SMMU are cache coherent with the
112 NOTE: this only applies to the SMMU itself, not masters connected
113 upstream of the SMMU.
115 calxeda,smmu-secure-config-access:
119 access to SMMU configuration registers. In this case non-secure aliases of
120 secure registers have to be used during SMMU configuration.
142 smmu ptw
143 - description: interface clock required to access smmu's registers
164 - nvidia,tegra194-smmu
177 /* SMMU with stream matching or stream indexing */
179 compatible = "arm,smmu-v1";
198 /* SMMU with stream matching */
200 compatible = "arm,smmu-v1";
226 compatible = "arm,mmu-500", "arm,smmu-v2";
242 ID each, but may master through multiple SMMU TBUs */
249 /* Qcom's arm,smmu-v2 implementation */
253 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";