Lines Matching +full:tightly +full:- +full:coupled

3 The NVIC provides an interrupt controller that is tightly coupled to
4 Cortex-M based processor cores.  The NVIC implemented on different SoCs
9 - compatible : should be one of:
10 	"arm,v6m-nvic"
11 	"arm,v7m-nvic"
12 	"arm,v8m-nvic"
13 - interrupt-controller : Identifies the node as an interrupt controller
14 - #interrupt-cells : Specifies the number of cells needed to encode an
21 - reg : Specifies base physical address(s) and size of the NVIC registers.
24 - arm,num-irq-priority-bits: The number of priority bits implemented by the
29 	intc: interrupt-controller@e000e100 {
30 		compatible = "arm,v7m-nvic";
31 		#interrupt-cells = <2>;
32 		#address-cells = <1>;
33 		interrupt-controller;
35 		arm,num-irq-priority-bits = <4>;