bindings/clock/rockchip%2Cclk-out.yaml

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/rockchip,clk-out.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Sugar Zhang <sugar.zhang@rock-chips.com>
13   This add support switch for clk-bidirection which located
16   which hard to addressed in one single clk driver. so, we add
20   clk usage (avoid high freq glitch), we set all clk out as disabled
21   (which means Input default for clk-bidrection) in the pre-stage,
22   such boot-loader or init by HW default. And then set a safety freq
23   before enable clk-out, such as "assign-clock-rates" or clk_set_rate
29       - rockchip,clk-out
34   "#clock-cells":
41   power-domains:
44   clock-output-names:
47   rockchip,bit-shift:
49     description: Defines the bit shift of clk out enable.
51   rockchip,bit-set-to-disable:
54       By default this clock sets the bit at bit-shift to enable the clock.
59   - compatible
60   - reg
61   - clocks
62   - "#clock-cells"
63   - clock-output-names
64   - rockchip,bit-shift
70   - |
71     mclkin_sai0: mclkin-sai0 {
72         compatible = "fixed-clock";
73         #clock-cells = <0>;
74         clock-frequency = <12288000>;
75         clock-output-names = "mclk_sai0_from_io";
78     mclkout_sai0: mclkout-sai0@ff040070 {
79         compatible = "rockchip,clk-out";
82         #clock-cells = <0>;
83         clock-output-names = "mclk_sai0_to_io";
84         rockchip,bit-shift = <4>;
88   - |
91         clock-names = "mclk";
92         assigned-clocks = <&mclkout_sai0>;
93         assigned-clock-rates = <12288000>;
94         pinctrl-names = "default";
95         pinctrl-0 = <&i2s0m0_mclk>;
99   - |
102         clock-names = "mclk";
103         assigned-clocks = <&cru CLK_SAI0>;
104         assigned-clock-parents = <&mclkin_sai0>;
105         pinctrl-names = "default";
106         pinctrl-0 = <&i2s0m0_mclk>;