arm/tegra/nvidia%2Ctegra20-pmc.yaml

4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
7 title: Tegra Power Management Controller (PMC)
34       pclk is the Tegra clock of that name and clk32k_in is 32KHz clock
35       input to Tegra.
46       Tegra PMC has clk_out_1, clk_out_2, and clk_out_3.
48       Tegra blink pad.
51       See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC
139           "APBDEV_PMC_SCRATCH53_0" of the Tegra K1 Technical Reference
173       match the powergates on the Tegra SoC. Each powergate node
174       represents a power-domain on the Tegra SoC that can be power-gated
175       by the Tegra PMC.
180       not every powergate is applicable to all Tegra devices and the following
182       Please refer to Tegra TRM for mode details on the powergate nodes to
183       use for each power-gate block inside Tegra.
244       This is a Pad configuration node. On Tegra SOCs a pad is a set of
289           include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
322     #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
323     #include <dt-bindings/soc/tegra-pmc.h>