Lines Matching full:are

5 RMW operations between CPUs (atomic operations on MMIO are not supported and
82 The non-RMW ops are (typically) regular LOADs and STOREs and are canonically
86 and are doing it wrong.
91   C Atomic-RMW-ops-are-atomic-WRT-atomic_set
142    these are limited to the arithmetic operations because those are
143    reversible. Bitops are irreversible and therefore the modified value
150  - misc; the special purpose operations that are commonly used and would,
152    are time critical and can, (typically) on LL/SC architectures, be more
155 All these operations are SMP atomic; that is, the operations (for a single
165  - non-RMW operations are unordered;
167  - RMW operations that have no return value are unordered;
169  - RMW operations that have a return value are fully ordered;
171  - RMW operations that are conditional are unordered on FAILURE,
180 Where 'unordered' is against other memory locations. Address dependencies are
183 Fully ordered primitives are ordered against everything prior and everything
197 accesses between the smp_mb__{before,after}_atomic() and the RMW op are not
203 provide full ordered atomics and these barriers are no-ops.
205 NOTE: when the atomic RmW ops are fully ordered, they should also imply a