Documentation/arm64/booting.rst

50 The device tree blob (dtb) must be placed on an 8-byte boundary and must
52 using blocks of up to 2 megabytes in size, it must not be placed within
53 any 2M region which must be mapped with any specific attributes.
103   little-endian and must be respected.  Where image_size is zero,
134 The Image must be placed text_offset bytes from a 2MB aligned base
138 At least image_size bytes from the start of the image must be free for
144 If an initrd/initramfs is passed to the kernel at boot, it must reside
153 Before jumping into the kernel, the following conditions must be met:
168   All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
170   The CPU must be in either EL2 (RECOMMENDED in order to have access to
175   The MMU must be off.
177   The instruction cache may be on or off, and must not hold any stale
180   The address range corresponding to the loaded kernel image must be
185   operations must be configured and may be enabled.
187   operations (not recommended) must be configured and disabled.
191   CNTFRQ must be programmed with the timer frequency and CNTVOFF must
193   kernel at EL1, CNTHCTL_EL2 must have EL1PCTEN (bit 0) set where
198   All CPUs to be booted by the kernel must be part of the same coherency
206   the kernel image will be entered must be initialised by software at a
209   - SCR_EL3.FIQ must have the same value across all CPUs the kernel is
211   - The value of SCR_EL3.FIQ must be the same as the one present at boot
217       - ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1.
218       - ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
219       - ICC_CTLR_EL3.PMHE (bit 6) must be set to the same value across
220         all CPUs the kernel is executing on, and must stay constant
225       - ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1
226       - ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
228   - The DT or ACPI tables must describe a GICv3 interrupt controller.
235       ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b0.
239       ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b0.
241   - The DT or ACPI tables must describe a GICv2 interrupt controller.
247     - SCR_EL3.APK (bit 16) must be initialised to 0b1
248     - SCR_EL3.API (bit 17) must be initialised to 0b1
252     - HCR_EL2.APK (bit 40) must be initialised to 0b1
253     - HCR_EL2.API (bit 41) must be initialised to 0b1
259     - CPTR_EL3.TAM (bit 30) must be initialised to 0b0
260     - CPTR_EL2.TAM (bit 30) must be initialised to 0b0
261     - AMCNTENSET0_EL0 must be initialised to 0b1111
262     - AMCNTENSET1_EL0 must be initialised to a platform specific value
268     - AMCNTENSET0_EL0 must be initialised to 0b1111
269     - AMCNTENSET1_EL0 must be initialised to a platform specific value
274 timers, coherency and system registers apply to all CPUs.  All CPUs must
280 - The primary CPU must jump directly to the first instruction of the
281   kernel image.  The device tree blob passed by this CPU must contain
288 - CPUs with a "spin-table" enable-method must have a 'cpu-release-addr'
294   device tree) polling their cpu-release-addr location, which must be
298   cpu-release-addr returns a non-zero value, the CPU must jump to this
300   value, so CPUs must convert the read value to their native endianness