Lines Matching refs:ramdacReg
125 RamDacRegRecPtr ramdacReg) in TIramdacRestore() argument
159 if (ramdacReg->DacRegs[TIDAC_PIXEL_VALID]) { in TIramdacRestore()
167 ramdacReg->DacRegs[TIDAC_PIXEL_N]); in TIramdacRestore()
169 ramdacReg->DacRegs[TIDAC_PIXEL_M]); in TIramdacRestore()
171 ramdacReg->DacRegs[TIDAC_PIXEL_P]); in TIramdacRestore()
185 if (ramdacReg->DacRegs[TIDAC_LOOP_VALID]) { in TIramdacRestore()
193 ramdacReg->DacRegs[TIDAC_LOOP_N]); in TIramdacRestore()
195 ramdacReg->DacRegs[TIDAC_LOOP_M]); in TIramdacRestore()
197 ramdacReg->DacRegs[TIDAC_LOOP_P]); in TIramdacRestore()
215 (*ramdacPtr->WriteData) (pScrn, ramdacReg->DAC[i]); in TIramdacRestore()
227 RamDacRegRecPtr ramdacReg) in TIramdacSave() argument
233 ramdacReg->DAC[i] = (*ramdacPtr->ReadData) (pScrn); in TIramdacSave()
237 ramdacReg->DacRegs[TIDAC_PIXEL_N] = in TIramdacSave()
240 ramdacReg->DacRegs[TIDAC_PIXEL_M] = in TIramdacSave()
243 ramdacReg->DacRegs[TIDAC_PIXEL_P] = in TIramdacSave()
248 ramdacReg->DacRegs[TIDAC_LOOP_N] = in TIramdacSave()
251 ramdacReg->DacRegs[TIDAC_LOOP_M] = in TIramdacSave()
254 ramdacReg->DacRegs[TIDAC_LOOP_P] = in TIramdacSave()
356 TIramdac3026SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr ramdacReg) in TIramdac3026SetBpp() argument
361 ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06; in TIramdac3026SetBpp()
362 ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x46; in TIramdac3026SetBpp()
363 ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x5c; in TIramdac3026SetBpp()
364 ramdacReg->DacRegs[TIDAC_clock_select] = 0x05; in TIramdac3026SetBpp()
365 ramdacReg->DacRegs[TIDAC_palette_page] = 0x00; in TIramdac3026SetBpp()
366 ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10; in TIramdac3026SetBpp()
367 ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C; in TIramdac3026SetBpp()
369 ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF; in TIramdac3026SetBpp()
370 ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF; in TIramdac3026SetBpp()
371 ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF; in TIramdac3026SetBpp()
372 ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF; in TIramdac3026SetBpp()
373 ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF; in TIramdac3026SetBpp()
374 ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF; in TIramdac3026SetBpp()
375 ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF; in TIramdac3026SetBpp()
376 ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00; in TIramdac3026SetBpp()
377 ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10; in TIramdac3026SetBpp()
378 ramdacReg->DacRegs[TIDAC_sense_test] = 0x00; in TIramdac3026SetBpp()
380 ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x06; in TIramdac3026SetBpp()
381 ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C; in TIramdac3026SetBpp()
382 ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x01; in TIramdac3026SetBpp()
384 ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00; in TIramdac3026SetBpp()
388 ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06; in TIramdac3026SetBpp()
389 ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x56; in TIramdac3026SetBpp()
390 ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x58; in TIramdac3026SetBpp()
391 ramdacReg->DacRegs[TIDAC_clock_select] = 0x25; in TIramdac3026SetBpp()
392 ramdacReg->DacRegs[TIDAC_palette_page] = 0x00; in TIramdac3026SetBpp()
393 ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00; in TIramdac3026SetBpp()
394 ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C; in TIramdac3026SetBpp()
396 ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF; in TIramdac3026SetBpp()
397 ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF; in TIramdac3026SetBpp()
398 ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF; in TIramdac3026SetBpp()
399 ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF; in TIramdac3026SetBpp()
400 ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF; in TIramdac3026SetBpp()
401 ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF; in TIramdac3026SetBpp()
402 ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF; in TIramdac3026SetBpp()
403 ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00; in TIramdac3026SetBpp()
404 ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10; in TIramdac3026SetBpp()
405 ramdacReg->DacRegs[TIDAC_sense_test] = 0x00; in TIramdac3026SetBpp()
406 ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00; in TIramdac3026SetBpp()
412 ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x07; in TIramdac3026SetBpp()
414 ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06; in TIramdac3026SetBpp()
417 ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x45; in TIramdac3026SetBpp()
420 ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x44; in TIramdac3026SetBpp()
424 ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x50; in TIramdac3026SetBpp()
425 ramdacReg->DacRegs[TIDAC_clock_select] = 0x15; in TIramdac3026SetBpp()
426 ramdacReg->DacRegs[TIDAC_palette_page] = 0x00; in TIramdac3026SetBpp()
427 ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00; in TIramdac3026SetBpp()
429 ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x54; in TIramdac3026SetBpp()
430 ramdacReg->DacRegs[TIDAC_clock_select] = 0x05; in TIramdac3026SetBpp()
431 ramdacReg->DacRegs[TIDAC_palette_page] = 0x00; in TIramdac3026SetBpp()
432 ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10; in TIramdac3026SetBpp()
434 ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C; in TIramdac3026SetBpp()
436 ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF; in TIramdac3026SetBpp()
437 ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF; in TIramdac3026SetBpp()
438 ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF; in TIramdac3026SetBpp()
439 ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF; in TIramdac3026SetBpp()
440 ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF; in TIramdac3026SetBpp()
441 ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF; in TIramdac3026SetBpp()
442 ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF; in TIramdac3026SetBpp()
443 ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00; in TIramdac3026SetBpp()
444 ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10; in TIramdac3026SetBpp()
445 ramdacReg->DacRegs[TIDAC_sense_test] = 0x00; in TIramdac3026SetBpp()
446 ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00; in TIramdac3026SetBpp()
450 ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06; in TIramdac3026SetBpp()
451 ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x80; in TIramdac3026SetBpp()
452 ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x4c; in TIramdac3026SetBpp()
453 ramdacReg->DacRegs[TIDAC_clock_select] = 0x05; in TIramdac3026SetBpp()
454 ramdacReg->DacRegs[TIDAC_palette_page] = 0x00; in TIramdac3026SetBpp()
455 ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10; in TIramdac3026SetBpp()
456 ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x1C; in TIramdac3026SetBpp()
458 ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF; in TIramdac3026SetBpp()
459 ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF; in TIramdac3026SetBpp()
460 ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF; in TIramdac3026SetBpp()
461 ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF; in TIramdac3026SetBpp()
462 ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF; in TIramdac3026SetBpp()
463 ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF; in TIramdac3026SetBpp()
464 ramdacReg->DacRegs[TIDAC_key_blue_low] = 0x00; in TIramdac3026SetBpp()
465 ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00; in TIramdac3026SetBpp()
466 ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x00; in TIramdac3026SetBpp()
467 ramdacReg->DacRegs[TIDAC_sense_test] = 0x00; in TIramdac3026SetBpp()
468 ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00; in TIramdac3026SetBpp()
474 TIramdac3030SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr ramdacReg) in TIramdac3030SetBpp() argument
479 ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06; in TIramdac3030SetBpp()
480 ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x46; in TIramdac3030SetBpp()
481 ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x5D; in TIramdac3030SetBpp()
482 ramdacReg->DacRegs[TIDAC_clock_select] = 0x05; in TIramdac3030SetBpp()
483 ramdacReg->DacRegs[TIDAC_palette_page] = 0x00; in TIramdac3030SetBpp()
484 ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10; in TIramdac3030SetBpp()
485 ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C; in TIramdac3030SetBpp()
487 ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF; in TIramdac3030SetBpp()
488 ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF; in TIramdac3030SetBpp()
489 ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF; in TIramdac3030SetBpp()
490 ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF; in TIramdac3030SetBpp()
491 ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF; in TIramdac3030SetBpp()
492 ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF; in TIramdac3030SetBpp()
493 ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF; in TIramdac3030SetBpp()
494 ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00; in TIramdac3030SetBpp()
495 ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10; in TIramdac3030SetBpp()
496 ramdacReg->DacRegs[TIDAC_sense_test] = 0x00; in TIramdac3030SetBpp()
498 ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x06; in TIramdac3030SetBpp()
499 ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C; in TIramdac3030SetBpp()
500 ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x01; in TIramdac3030SetBpp()
502 ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00; in TIramdac3030SetBpp()
506 ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06; in TIramdac3030SetBpp()
507 ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x56; in TIramdac3030SetBpp()
508 ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x58; in TIramdac3030SetBpp()
509 ramdacReg->DacRegs[TIDAC_clock_select] = 0x25; in TIramdac3030SetBpp()
510 ramdacReg->DacRegs[TIDAC_palette_page] = 0x00; in TIramdac3030SetBpp()
511 ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00; in TIramdac3030SetBpp()
512 ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C; in TIramdac3030SetBpp()
514 ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF; in TIramdac3030SetBpp()
515 ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF; in TIramdac3030SetBpp()
516 ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF; in TIramdac3030SetBpp()
517 ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF; in TIramdac3030SetBpp()
518 ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF; in TIramdac3030SetBpp()
519 ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF; in TIramdac3030SetBpp()
520 ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF; in TIramdac3030SetBpp()
521 ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00; in TIramdac3030SetBpp()
522 ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10; in TIramdac3030SetBpp()
523 ramdacReg->DacRegs[TIDAC_sense_test] = 0x00; in TIramdac3030SetBpp()
524 ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00; in TIramdac3030SetBpp()
530 ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x07; in TIramdac3030SetBpp()
532 ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06; in TIramdac3030SetBpp()
535 ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x45; in TIramdac3030SetBpp()
538 ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x44; in TIramdac3030SetBpp()
542 ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x50; in TIramdac3030SetBpp()
543 ramdacReg->DacRegs[TIDAC_clock_select] = 0x15; in TIramdac3030SetBpp()
544 ramdacReg->DacRegs[TIDAC_palette_page] = 0x00; in TIramdac3030SetBpp()
545 ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00; in TIramdac3030SetBpp()
547 ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x55; in TIramdac3030SetBpp()
548 ramdacReg->DacRegs[TIDAC_clock_select] = 0x85; in TIramdac3030SetBpp()
549 ramdacReg->DacRegs[TIDAC_palette_page] = 0x00; in TIramdac3030SetBpp()
550 ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10; in TIramdac3030SetBpp()
552 ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C; in TIramdac3030SetBpp()
554 ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF; in TIramdac3030SetBpp()
555 ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF; in TIramdac3030SetBpp()
556 ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF; in TIramdac3030SetBpp()
557 ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF; in TIramdac3030SetBpp()
558 ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF; in TIramdac3030SetBpp()
559 ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF; in TIramdac3030SetBpp()
560 ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF; in TIramdac3030SetBpp()
561 ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00; in TIramdac3030SetBpp()
562 ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10; in TIramdac3030SetBpp()
563 ramdacReg->DacRegs[TIDAC_sense_test] = 0x00; in TIramdac3030SetBpp()
564 ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00; in TIramdac3030SetBpp()
568 ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06; in TIramdac3030SetBpp()
569 ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x80; in TIramdac3030SetBpp()
570 ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x4d; in TIramdac3030SetBpp()
571 ramdacReg->DacRegs[TIDAC_clock_select] = 0x05; in TIramdac3030SetBpp()
572 ramdacReg->DacRegs[TIDAC_palette_page] = 0x00; in TIramdac3030SetBpp()
573 ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10; in TIramdac3030SetBpp()
574 ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x1C; in TIramdac3030SetBpp()
576 ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF; in TIramdac3030SetBpp()
577 ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF; in TIramdac3030SetBpp()
578 ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF; in TIramdac3030SetBpp()
579 ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF; in TIramdac3030SetBpp()
580 ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF; in TIramdac3030SetBpp()
581 ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF; in TIramdac3030SetBpp()
582 ramdacReg->DacRegs[TIDAC_key_blue_low] = 0x00; in TIramdac3030SetBpp()
583 ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00; in TIramdac3030SetBpp()
584 ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x00; in TIramdac3030SetBpp()
585 ramdacReg->DacRegs[TIDAC_sense_test] = 0x00; in TIramdac3030SetBpp()
586 ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00; in TIramdac3030SetBpp()