Lines Matching +full:vco +full:- +full:hz
29 #include <xorg-config.h>
46 TIramdacCalculateMNPForClock(unsigned long RefClock, /* In 100Hz units */ in TIramdacCalculateMNPForClock()
47 unsigned long ReqClock, /* In 100Hz units */ in TIramdacCalculateMNPForClock()
49 unsigned long MinClock, /* Min VCO rating */ in TIramdacCalculateMNPForClock()
50 unsigned long MaxClock, /* Max VCO rating */ in TIramdacCalculateMNPForClock()
58 double VCO, IntRef = (double) RefClock; in TIramdacCalculateMNPForClock() local
69 * ActualClock = VCO / 2 ^ p in TIramdacCalculateMNPForClock()
70 * Choose p so that TI_MIN_VCO_FREQ <= VCO <= TI_MAX_VCO_FREQ in TIramdacCalculateMNPForClock()
74 VCO = (double) ReqClock; in TIramdacCalculateMNPForClock()
75 for (p = 0; p < 3 && VCO < TI_MIN_VCO_FREQ; (p)++) in TIramdacCalculateMNPForClock()
76 VCO *= 2.0; in TIramdacCalculateMNPForClock()
79 * We avoid doing multiplications by ( 65 - n ), in TIramdacCalculateMNPForClock()
80 * and add an increment instead - this keeps any error small. in TIramdacCalculateMNPForClock()
82 inc_m = VCO / (IntRef * 8.0); in TIramdacCalculateMNPForClock()
87 /* Initial amount of error for an integer - impossibly large */ in TIramdacCalculateMNPForClock()
90 /* Search for the closest INTEGER value of ( 65 - m ) */ in TIramdacCalculateMNPForClock()
93 /* Ignore values of ( 65 - m ) which we can't use */ in TIramdacCalculateMNPForClock()
101 if ((calc_m - (int) calc_m) < m_err) { in TIramdacCalculateMNPForClock()
102 m_err = calc_m - (int) calc_m; in TIramdacCalculateMNPForClock()
108 /* 65 - ( 65 - x ) = x */ in TIramdacCalculateMNPForClock()
109 *rM = 65 - best_m; in TIramdacCalculateMNPForClock()
110 *rN = 65 - best_n; in TIramdacCalculateMNPForClock()
114 VCO = 8.0 * IntRef * best_m / best_n; in TIramdacCalculateMNPForClock()
115 ActualClock = VCO / (1 << p); in TIramdacCalculateMNPForClock()
118 ActualClock, VCO, *rN, *rM, *rP); in TIramdacCalculateMNPForClock()
151 (*ramdacPtr->WriteDAC) (pScrn, TIDAC_clock_ctrl, 0, 0x30); in TIramdacRestore()
152 (*ramdacPtr->WriteDAC) (pScrn, TIDAC_clock_ctrl, 0, 0x38); in TIramdacRestore()
159 if (ramdacReg->DacRegs[TIDAC_PIXEL_VALID]) { in TIramdacRestore()
161 (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0x22); in TIramdacRestore()
162 (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_pixel_data, 0, 0x3c); in TIramdacRestore()
165 (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0); in TIramdacRestore()
166 (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_pixel_data, 0, in TIramdacRestore()
167 ramdacReg->DacRegs[TIDAC_PIXEL_N]); in TIramdacRestore()
168 (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_pixel_data, 0, in TIramdacRestore()
169 ramdacReg->DacRegs[TIDAC_PIXEL_M]); in TIramdacRestore()
170 (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_pixel_data, 0, in TIramdacRestore()
171 ramdacReg->DacRegs[TIDAC_PIXEL_P]); in TIramdacRestore()
176 status = (*ramdacPtr->ReadDAC) (pScrn, TIDAC_pll_pixel_data); in TIramdacRestore()
177 } while ((!(status & 0x40)) && (--i)); in TIramdacRestore()
179 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, in TIramdacRestore()
185 if (ramdacReg->DacRegs[TIDAC_LOOP_VALID]) { in TIramdacRestore()
187 (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0x22); in TIramdacRestore()
188 (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_loop_data, 0, 0x70); in TIramdacRestore()
191 (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0); in TIramdacRestore()
192 (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_loop_data, 0, in TIramdacRestore()
193 ramdacReg->DacRegs[TIDAC_LOOP_N]); in TIramdacRestore()
194 (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_loop_data, 0, in TIramdacRestore()
195 ramdacReg->DacRegs[TIDAC_LOOP_M]); in TIramdacRestore()
196 (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_loop_data, 0, in TIramdacRestore()
197 ramdacReg->DacRegs[TIDAC_LOOP_P]); in TIramdacRestore()
202 status = (*ramdacPtr->ReadDAC) (pScrn, TIDAC_pll_loop_data); in TIramdacRestore()
203 } while ((!(status & 0x40)) && (--i)); in TIramdacRestore()
205 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, in TIramdacRestore()
212 (*ramdacPtr->WriteAddress) (pScrn, 0); in TIramdacRestore()
215 (*ramdacPtr->WriteData) (pScrn, ramdacReg->DAC[i]); in TIramdacRestore()
217 (*ramdacPtr->WriteData) (pScrn, 0); in TIramdacRestore()
218 (*ramdacPtr->WriteData) (pScrn, 0); in TIramdacRestore()
219 (*ramdacPtr->WriteData) (pScrn, 0); in TIramdacRestore()
221 (*ramdacPtr->WriteData) (pScrn, 0xff); in TIramdacRestore()
231 (*ramdacPtr->ReadAddress) (pScrn, 0); in TIramdacSave()
233 ramdacReg->DAC[i] = (*ramdacPtr->ReadData) (pScrn); in TIramdacSave()
236 (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0); in TIramdacSave()
237 ramdacReg->DacRegs[TIDAC_PIXEL_N] = in TIramdacSave()
238 (*ramdacPtr->ReadDAC) (pScrn, TIDAC_pll_pixel_data); in TIramdacSave()
239 (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0x11); in TIramdacSave()
240 ramdacReg->DacRegs[TIDAC_PIXEL_M] = in TIramdacSave()
241 (*ramdacPtr->ReadDAC) (pScrn, TIDAC_pll_pixel_data); in TIramdacSave()
242 (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0x22); in TIramdacSave()
243 ramdacReg->DacRegs[TIDAC_PIXEL_P] = in TIramdacSave()
244 (*ramdacPtr->ReadDAC) (pScrn, TIDAC_pll_pixel_data); in TIramdacSave()
247 (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0); in TIramdacSave()
248 ramdacReg->DacRegs[TIDAC_LOOP_N] = in TIramdacSave()
249 (*ramdacPtr->ReadDAC) (pScrn, TIDAC_pll_loop_data); in TIramdacSave()
250 (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0x11); in TIramdacSave()
251 ramdacReg->DacRegs[TIDAC_LOOP_M] = in TIramdacSave()
252 (*ramdacPtr->ReadDAC) (pScrn, TIDAC_pll_loop_data); in TIramdacSave()
253 (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0x22); in TIramdacSave()
254 ramdacReg->DacRegs[TIDAC_LOOP_P] = in TIramdacSave()
255 (*ramdacPtr->ReadDAC) (pScrn, TIDAC_pll_loop_data); in TIramdacSave()
286 int TIramdac_ID = -1; in TIramdacProbe()
291 rev = (*ramdacPtr->ReadDAC) (pScrn, TIDAC_rev); in TIramdacProbe()
292 id = (*ramdacPtr->ReadDAC) (pScrn, TIDAC_id); in TIramdacProbe()
295 (*ramdacPtr->WriteDAC) (pScrn, ~rev, 0, TIDAC_rev); in TIramdacProbe()
296 (*ramdacPtr->WriteDAC) (pScrn, ~id, 0, TIDAC_id); in TIramdacProbe()
297 rev2 = (*ramdacPtr->ReadDAC) (pScrn, TIDAC_rev); in TIramdacProbe()
298 id2 = (*ramdacPtr->ReadDAC) (pScrn, TIDAC_id); in TIramdacProbe()
311 (*ramdacPtr->WriteDAC) (pScrn, rev, 0, TIDAC_rev); in TIramdacProbe()
312 (*ramdacPtr->WriteDAC) (pScrn, id, 0, TIDAC_id); in TIramdacProbe()
314 if (TIramdac_ID == -1) { in TIramdacProbe()
315 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, in TIramdacProbe()
320 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, in TIramdacProbe()
325 for (i = 0; ramdacs[i].token != -1; i++) { in TIramdacProbe()
331 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, in TIramdacProbe()
339 ramdacHelperPtr->SetBpp = TIramdac3030SetBpp; in TIramdacProbe()
340 ramdacHelperPtr->HWCursorInit = TIramdacHWCursorInit; in TIramdacProbe()
343 ramdacHelperPtr->SetBpp = TIramdac3026SetBpp; in TIramdacProbe()
344 ramdacHelperPtr->HWCursorInit = TIramdacHWCursorInit; in TIramdacProbe()
347 ramdacPtr->RamDacType = TIramdac_ID; in TIramdacProbe()
348 ramdacHelperPtr->RamDacType = TIramdac_ID; in TIramdacProbe()
349 ramdacHelperPtr->Save = TIramdacSave; in TIramdacProbe()
350 ramdacHelperPtr->Restore = TIramdacRestore; in TIramdacProbe()
358 switch (pScrn->bitsPerPixel) { in TIramdac3026SetBpp()
361 ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06; in TIramdac3026SetBpp()
362 ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x46; in TIramdac3026SetBpp()
363 ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x5c; in TIramdac3026SetBpp()
364 ramdacReg->DacRegs[TIDAC_clock_select] = 0x05; in TIramdac3026SetBpp()
365 ramdacReg->DacRegs[TIDAC_palette_page] = 0x00; in TIramdac3026SetBpp()
366 ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10; in TIramdac3026SetBpp()
367 ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C; in TIramdac3026SetBpp()
369 ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF; in TIramdac3026SetBpp()
370 ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF; in TIramdac3026SetBpp()
371 ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF; in TIramdac3026SetBpp()
372 ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF; in TIramdac3026SetBpp()
373 ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF; in TIramdac3026SetBpp()
374 ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF; in TIramdac3026SetBpp()
375 ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF; in TIramdac3026SetBpp()
376 ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00; in TIramdac3026SetBpp()
377 ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10; in TIramdac3026SetBpp()
378 ramdacReg->DacRegs[TIDAC_sense_test] = 0x00; in TIramdac3026SetBpp()
379 if (pScrn->overlayFlags & OVERLAY_8_32_PLANAR) { in TIramdac3026SetBpp()
380 ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x06; in TIramdac3026SetBpp()
381 ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C; in TIramdac3026SetBpp()
382 ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x01; in TIramdac3026SetBpp()
384 ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00; in TIramdac3026SetBpp()
388 ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06; in TIramdac3026SetBpp()
389 ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x56; in TIramdac3026SetBpp()
390 ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x58; in TIramdac3026SetBpp()
391 ramdacReg->DacRegs[TIDAC_clock_select] = 0x25; in TIramdac3026SetBpp()
392 ramdacReg->DacRegs[TIDAC_palette_page] = 0x00; in TIramdac3026SetBpp()
393 ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00; in TIramdac3026SetBpp()
394 ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C; in TIramdac3026SetBpp()
396 ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF; in TIramdac3026SetBpp()
397 ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF; in TIramdac3026SetBpp()
398 ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF; in TIramdac3026SetBpp()
399 ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF; in TIramdac3026SetBpp()
400 ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF; in TIramdac3026SetBpp()
401 ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF; in TIramdac3026SetBpp()
402 ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF; in TIramdac3026SetBpp()
403 ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00; in TIramdac3026SetBpp()
404 ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10; in TIramdac3026SetBpp()
405 ramdacReg->DacRegs[TIDAC_sense_test] = 0x00; in TIramdac3026SetBpp()
406 ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00; in TIramdac3026SetBpp()
412 ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x07; in TIramdac3026SetBpp()
414 ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06; in TIramdac3026SetBpp()
416 if (pScrn->depth == 16) { in TIramdac3026SetBpp()
417 ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x45; in TIramdac3026SetBpp()
420 ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x44; in TIramdac3026SetBpp()
424 ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x50; in TIramdac3026SetBpp()
425 ramdacReg->DacRegs[TIDAC_clock_select] = 0x15; in TIramdac3026SetBpp()
426 ramdacReg->DacRegs[TIDAC_palette_page] = 0x00; in TIramdac3026SetBpp()
427 ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00; in TIramdac3026SetBpp()
429 ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x54; in TIramdac3026SetBpp()
430 ramdacReg->DacRegs[TIDAC_clock_select] = 0x05; in TIramdac3026SetBpp()
431 ramdacReg->DacRegs[TIDAC_palette_page] = 0x00; in TIramdac3026SetBpp()
432 ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10; in TIramdac3026SetBpp()
434 ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C; in TIramdac3026SetBpp()
436 ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF; in TIramdac3026SetBpp()
437 ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF; in TIramdac3026SetBpp()
438 ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF; in TIramdac3026SetBpp()
439 ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF; in TIramdac3026SetBpp()
440 ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF; in TIramdac3026SetBpp()
441 ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF; in TIramdac3026SetBpp()
442 ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF; in TIramdac3026SetBpp()
443 ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00; in TIramdac3026SetBpp()
444 ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10; in TIramdac3026SetBpp()
445 ramdacReg->DacRegs[TIDAC_sense_test] = 0x00; in TIramdac3026SetBpp()
446 ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00; in TIramdac3026SetBpp()
450 ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06; in TIramdac3026SetBpp()
451 ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x80; in TIramdac3026SetBpp()
452 ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x4c; in TIramdac3026SetBpp()
453 ramdacReg->DacRegs[TIDAC_clock_select] = 0x05; in TIramdac3026SetBpp()
454 ramdacReg->DacRegs[TIDAC_palette_page] = 0x00; in TIramdac3026SetBpp()
455 ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10; in TIramdac3026SetBpp()
456 ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x1C; in TIramdac3026SetBpp()
458 ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF; in TIramdac3026SetBpp()
459 ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF; in TIramdac3026SetBpp()
460 ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF; in TIramdac3026SetBpp()
461 ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF; in TIramdac3026SetBpp()
462 ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF; in TIramdac3026SetBpp()
463 ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF; in TIramdac3026SetBpp()
464 ramdacReg->DacRegs[TIDAC_key_blue_low] = 0x00; in TIramdac3026SetBpp()
465 ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00; in TIramdac3026SetBpp()
466 ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x00; in TIramdac3026SetBpp()
467 ramdacReg->DacRegs[TIDAC_sense_test] = 0x00; in TIramdac3026SetBpp()
468 ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00; in TIramdac3026SetBpp()
476 switch (pScrn->bitsPerPixel) { in TIramdac3030SetBpp()
479 ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06; in TIramdac3030SetBpp()
480 ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x46; in TIramdac3030SetBpp()
481 ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x5D; in TIramdac3030SetBpp()
482 ramdacReg->DacRegs[TIDAC_clock_select] = 0x05; in TIramdac3030SetBpp()
483 ramdacReg->DacRegs[TIDAC_palette_page] = 0x00; in TIramdac3030SetBpp()
484 ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10; in TIramdac3030SetBpp()
485 ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C; in TIramdac3030SetBpp()
487 ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF; in TIramdac3030SetBpp()
488 ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF; in TIramdac3030SetBpp()
489 ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF; in TIramdac3030SetBpp()
490 ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF; in TIramdac3030SetBpp()
491 ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF; in TIramdac3030SetBpp()
492 ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF; in TIramdac3030SetBpp()
493 ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF; in TIramdac3030SetBpp()
494 ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00; in TIramdac3030SetBpp()
495 ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10; in TIramdac3030SetBpp()
496 ramdacReg->DacRegs[TIDAC_sense_test] = 0x00; in TIramdac3030SetBpp()
497 if (pScrn->overlayFlags & OVERLAY_8_32_PLANAR) { in TIramdac3030SetBpp()
498 ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x06; in TIramdac3030SetBpp()
499 ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C; in TIramdac3030SetBpp()
500 ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x01; in TIramdac3030SetBpp()
502 ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00; in TIramdac3030SetBpp()
506 ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06; in TIramdac3030SetBpp()
507 ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x56; in TIramdac3030SetBpp()
508 ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x58; in TIramdac3030SetBpp()
509 ramdacReg->DacRegs[TIDAC_clock_select] = 0x25; in TIramdac3030SetBpp()
510 ramdacReg->DacRegs[TIDAC_palette_page] = 0x00; in TIramdac3030SetBpp()
511 ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00; in TIramdac3030SetBpp()
512 ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C; in TIramdac3030SetBpp()
514 ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF; in TIramdac3030SetBpp()
515 ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF; in TIramdac3030SetBpp()
516 ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF; in TIramdac3030SetBpp()
517 ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF; in TIramdac3030SetBpp()
518 ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF; in TIramdac3030SetBpp()
519 ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF; in TIramdac3030SetBpp()
520 ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF; in TIramdac3030SetBpp()
521 ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00; in TIramdac3030SetBpp()
522 ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10; in TIramdac3030SetBpp()
523 ramdacReg->DacRegs[TIDAC_sense_test] = 0x00; in TIramdac3030SetBpp()
524 ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00; in TIramdac3030SetBpp()
530 ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x07; in TIramdac3030SetBpp()
532 ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06; in TIramdac3030SetBpp()
534 if (pScrn->depth == 16) { in TIramdac3030SetBpp()
535 ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x45; in TIramdac3030SetBpp()
538 ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x44; in TIramdac3030SetBpp()
542 ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x50; in TIramdac3030SetBpp()
543 ramdacReg->DacRegs[TIDAC_clock_select] = 0x15; in TIramdac3030SetBpp()
544 ramdacReg->DacRegs[TIDAC_palette_page] = 0x00; in TIramdac3030SetBpp()
545 ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00; in TIramdac3030SetBpp()
547 ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x55; in TIramdac3030SetBpp()
548 ramdacReg->DacRegs[TIDAC_clock_select] = 0x85; in TIramdac3030SetBpp()
549 ramdacReg->DacRegs[TIDAC_palette_page] = 0x00; in TIramdac3030SetBpp()
550 ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10; in TIramdac3030SetBpp()
552 ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C; in TIramdac3030SetBpp()
554 ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF; in TIramdac3030SetBpp()
555 ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF; in TIramdac3030SetBpp()
556 ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF; in TIramdac3030SetBpp()
557 ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF; in TIramdac3030SetBpp()
558 ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF; in TIramdac3030SetBpp()
559 ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF; in TIramdac3030SetBpp()
560 ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF; in TIramdac3030SetBpp()
561 ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00; in TIramdac3030SetBpp()
562 ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10; in TIramdac3030SetBpp()
563 ramdacReg->DacRegs[TIDAC_sense_test] = 0x00; in TIramdac3030SetBpp()
564 ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00; in TIramdac3030SetBpp()
568 ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06; in TIramdac3030SetBpp()
569 ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x80; in TIramdac3030SetBpp()
570 ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x4d; in TIramdac3030SetBpp()
571 ramdacReg->DacRegs[TIDAC_clock_select] = 0x05; in TIramdac3030SetBpp()
572 ramdacReg->DacRegs[TIDAC_palette_page] = 0x00; in TIramdac3030SetBpp()
573 ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10; in TIramdac3030SetBpp()
574 ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x1C; in TIramdac3030SetBpp()
576 ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF; in TIramdac3030SetBpp()
577 ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF; in TIramdac3030SetBpp()
578 ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF; in TIramdac3030SetBpp()
579 ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF; in TIramdac3030SetBpp()
580 ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF; in TIramdac3030SetBpp()
581 ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF; in TIramdac3030SetBpp()
582 ramdacReg->DacRegs[TIDAC_key_blue_low] = 0x00; in TIramdac3030SetBpp()
583 ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00; in TIramdac3030SetBpp()
584 ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x00; in TIramdac3030SetBpp()
585 ramdacReg->DacRegs[TIDAC_sense_test] = 0x00; in TIramdac3030SetBpp()
586 ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00; in TIramdac3030SetBpp()
596 /* Enable cursor - X11 mode */ in TIramdacShowCursor()
597 (*ramdacPtr->WriteDAC) (pScrn, TIDAC_ind_curs_ctrl, 0, 0x03); in TIramdacShowCursor()
605 /* Disable cursor - X11 mode */ in TIramdacHideCursor()
606 (*ramdacPtr->WriteDAC) (pScrn, TIDAC_ind_curs_ctrl, 0, 0x00); in TIramdacHideCursor()
617 (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_XLOW, 0, x & 0xff); in TIramdacSetCursorPosition()
618 (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_XHIGH, 0, (x >> 8) & 0x0f); in TIramdacSetCursorPosition()
619 (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_YLOW, 0, y & 0xff); in TIramdacSetCursorPosition()
620 (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_YHIGH, 0, (y >> 8) & 0x0f); in TIramdacSetCursorPosition()
629 (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_WRITE_ADDR, 0, 1); in TIramdacSetCursorColors()
630 (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_COLOR, 0, in TIramdacSetCursorColors()
632 (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_COLOR, 0, in TIramdacSetCursorColors()
634 (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_COLOR, 0, (bg & 0x000000ff)); in TIramdacSetCursorColors()
637 (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_WRITE_ADDR, 0, 2); in TIramdacSetCursorColors()
638 (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_COLOR, 0, in TIramdacSetCursorColors()
640 (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_COLOR, 0, in TIramdacSetCursorColors()
642 (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_COLOR, 0, (fg & 0x000000ff)); in TIramdacSetCursorColors()
652 (*ramdacPtr->WriteDAC) (pScrn, TIDAC_ind_curs_ctrl, 0, 0x00); in TIramdacLoadCursorImage()
654 (*ramdacPtr->WriteDAC) (pScrn, TIDAC_INDEX, 0x00, 0x00); in TIramdacLoadCursorImage()
656 while (i--) { in TIramdacLoadCursorImage()
658 (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_RAM_DATA, 0, *(src++)); in TIramdacLoadCursorImage()
672 infoPtr->MaxWidth = 64; in TIramdacHWCursorInit()
673 infoPtr->MaxHeight = 64; in TIramdacHWCursorInit()
674 infoPtr->Flags = HARDWARE_CURSOR_BIT_ORDER_MSBFIRST | in TIramdacHWCursorInit()
677 infoPtr->SetCursorColors = TIramdacSetCursorColors; in TIramdacHWCursorInit()
678 infoPtr->SetCursorPosition = TIramdacSetCursorPosition; in TIramdacHWCursorInit()
679 infoPtr->LoadCursorImageCheck = TIramdacLoadCursorImage; in TIramdacHWCursorInit()
680 infoPtr->HideCursor = TIramdacHideCursor; in TIramdacHWCursorInit()
681 infoPtr->ShowCursor = TIramdacShowCursor; in TIramdacHWCursorInit()
682 infoPtr->UseHWCursor = TIramdacUseHWCursor; in TIramdacHWCursorInit()
693 if (pScrn->depth == 16) { in TIramdacLoadPalette()
696 (*hwp->WriteAddress) (pScrn, index << 2); in TIramdacLoadPalette()
697 (*hwp->WriteData) (pScrn, colors[index >> 1].red); in TIramdacLoadPalette()
698 (*hwp->WriteData) (pScrn, colors[index].green); in TIramdacLoadPalette()
699 (*hwp->WriteData) (pScrn, colors[index >> 1].blue); in TIramdacLoadPalette()
702 (*hwp->WriteAddress) (pScrn, index << 3); in TIramdacLoadPalette()
703 (*hwp->WriteData) (pScrn, colors[index].red); in TIramdacLoadPalette()
704 (*hwp->WriteData) (pScrn, colors[(index << 1) + 1].green); in TIramdacLoadPalette()
705 (*hwp->WriteData) (pScrn, colors[index].blue); in TIramdacLoadPalette()
710 shift = (pScrn->depth == 15) ? 3 : 0; in TIramdacLoadPalette()
714 (*hwp->WriteAddress) (pScrn, index << shift); in TIramdacLoadPalette()
715 (*hwp->WriteData) (pScrn, colors[index].red); in TIramdacLoadPalette()
716 (*hwp->WriteData) (pScrn, colors[index].green); in TIramdacLoadPalette()
717 (*hwp->WriteData) (pScrn, colors[index].blue); in TIramdacLoadPalette()