125 static si_info_t *si_doattach(si_info_t *sii, uint devid, osl_t *osh, volatile void *regs,
127 static bool si_buscore_prep(si_info_t *sii, uint bustype, uint devid, void *sdh);
128 static bool si_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype, uint32 savewin,
174 	si_info_t *sii;  in si_attach()  local
178 	if ((sii = MALLOCZ_NOPERSIST(osh, sizeof(si_info_t))) == NULL) {  in si_attach()
187 		MFREE(osh, sii, sizeof(si_info_t));  in si_attach()
190 	sii->cores_info = cores_info;  in si_attach()
192 	if (si_doattach(sii, devid, osh, regs, bustype, sdh, vars, varsz) == NULL) {  in si_attach()
193 		MFREE(osh, sii, sizeof(si_info_t));  in si_attach()
197 	sii->vars = vars ? *vars : NULL;  in si_attach()
198 	sii->varsz = varsz ? *varsz : 0;  in si_attach()
200 	return (si_t *)sii;  in si_attach()
277 si_buscore_prep(si_info_t *sii, uint bustype, uint devid, void *sdh)  in si_buscore_prep()  argument
283 		sii->memseg = TRUE;  in si_buscore_prep()
344 	si_info_t *sii = SI_INFO(sih);  in si_get_pmu_reg_addr()  local
349 	if (!(sii->pub.cccaps & CC_CAP_PMU)) {  in si_get_pmu_reg_addr()
352 	if (AOB_ENAB(&sii->pub)) {  in si_get_pmu_reg_addr()
356 		origidx = sii->curidx;  in si_get_pmu_reg_addr()
357 		pmucoreidx = si_findcoreidx(&sii->pub, PMU_CORE_ID, 0);  in si_get_pmu_reg_addr()
358 		pmu = si_setcoreidx(&sii->pub, pmucoreidx);  in si_get_pmu_reg_addr()
370 si_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype, uint32 savewin,  in si_buscore_setup()  argument
373 	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;  in si_buscore_setup()
377 	struct si_pub *sih = &sii->pub;  in si_buscore_setup()
381 	si_slave_wrapper_add(&sii->pub);  in si_buscore_setup()
383 	sii->curidx = 0;  in si_buscore_setup()
385 	cc = si_setcoreidx(&sii->pub, SI_CC_IDX);  in si_buscore_setup()
389 	sii->pub.ccrev = (int)si_corerev(&sii->pub);  in si_buscore_setup()
392 	if (CCREV(sii->pub.ccrev) >= 11) {  in si_buscore_setup()
394 		if (sii->pub.chip != CYW55500_CHIP_ID &&  in si_buscore_setup()
395 		    sii->pub.chip != CYW55560_CHIP_ID) {  in si_buscore_setup()
396 			sii->pub.chipst = R_REG(sii->osh, &cc->chipstatus);  in si_buscore_setup()
402 		sii->pub.cccaps = R_REG(sii->osh, &cc->capabilities);  in si_buscore_setup()
404 		if (CCREV(sii->pub.ccrev) >= 35)  in si_buscore_setup()
405 			sii->pub.cccaps_ext = R_REG(sii->osh, &cc->capabilities_ext);  in si_buscore_setup()
408 		if (sii->pub.cccaps & CC_CAP_PMU) {  in si_buscore_setup()
409 			if (AOB_ENAB(&sii->pub)) {  in si_buscore_setup()
412 				struct si_pub *sih = &sii->pub;  in si_buscore_setup()
414 				pmucoreidx = si_findcoreidx(&sii->pub, PMU_CORE_ID, 0);  in si_buscore_setup()
420 				pmu = si_setcoreidx(&sii->pub, pmucoreidx);  in si_buscore_setup()
421 				sii->pub.pmucaps = R_REG(sii->osh, &pmu->pmucapabilities);  in si_buscore_setup()
422 				si_setcoreidx(&sii->pub, SI_CC_IDX);  in si_buscore_setup()
424 				sii->pub.gcirev = si_corereg(sih, GCI_CORE_IDX(sih),  in si_buscore_setup()
428 				sii->pub.pmucaps = R_REG(sii->osh, &cc->pmucapabilities);  in si_buscore_setup()
430 			sii->pub.pmurev = sii->pub.pmucaps & PCAP_REV_MASK;  in si_buscore_setup()
435 		CCREV(sii->pub.ccrev), sii->pub.cccaps, sii->pub.chipst, sii->pub.pmurev,  in si_buscore_setup()
436 		sii->pub.pmucaps));  in si_buscore_setup()
439 	sii->pub.buscoretype = NODEV_CORE_ID;  in si_buscore_setup()
440 	sii->pub.buscorerev = (uint)NOREV;  in si_buscore_setup()
441 	sii->pub.buscoreidx = BADIDX;  in si_buscore_setup()
447 	for (i = 0; i < sii->numcores; i++) {  in si_buscore_setup()
450 		si_setcoreidx(&sii->pub, i);  in si_buscore_setup()
451 		cid = si_coreid(&sii->pub);  in si_buscore_setup()
452 		crev = si_corerev(&sii->pub);  in si_buscore_setup()
456 			i, cid, crev, sii->coresba[i], sii->coresba_size[i],  in si_buscore_setup()
457 			OSL_OBFUSCATE_BUF(sii->regs[i])));  in si_buscore_setup()
485 			sii->pub.buscorerev = crev;  in si_buscore_setup()
486 			sii->pub.buscoretype = cid;  in si_buscore_setup()
487 			sii->pub.buscoreidx = i;  in si_buscore_setup()
494 			sii->pub.buscorerev = crev;  in si_buscore_setup()
495 			sii->pub.buscoretype = cid;  in si_buscore_setup()
496 			sii->pub.buscoreidx = i;  in si_buscore_setup()
509 			sii->pub.buscoretype = PCIE2_CORE_ID;  in si_buscore_setup()
511 			sii->pub.buscoretype = PCIE_CORE_ID;  in si_buscore_setup()
512 		sii->pub.buscorerev = pcierev;  in si_buscore_setup()
513 		sii->pub.buscoreidx = pcieidx;  in si_buscore_setup()
520 		sii->pub.buscoretype = PCI_CORE_ID;  in si_buscore_setup()
521 		sii->pub.buscorerev = pcirev;  in si_buscore_setup()
522 		sii->pub.buscoreidx = pciidx;  in si_buscore_setup()
525 			sii->pub.buscoretype = PCIE2_CORE_ID;  in si_buscore_setup()
527 			sii->pub.buscoretype = PCIE_CORE_ID;  in si_buscore_setup()
528 		sii->pub.buscorerev = pcierev;  in si_buscore_setup()
529 		sii->pub.buscoreidx = pcieidx;  in si_buscore_setup()
533 	SI_VMSG(("Buscore id/type/rev %d/0x%x/%d\n", sii->pub.buscoreidx, sii->pub.buscoretype,  in si_buscore_setup()
534 	         sii->pub.buscorerev));  in si_buscore_setup()
541 		if (si_setcore(&sii->pub, ARM7S_CORE_ID, 0) ||  in si_buscore_setup()
542 		    si_setcore(&sii->pub, ARMCM3_CORE_ID, 0))  in si_buscore_setup()
543 			si_core_disable(&sii->pub, 0);  in si_buscore_setup()
548 	si_setcoreidx(&sii->pub, *origidx);  in si_buscore_setup()
556 	si_info_t *sii = SI_INFO(sih);  in si_chipid()  local
558 	return (sii->chipnew) ? sii->chipnew : sih->chip;  in si_chipid()
565 	si_info_t *sii = SI_INFO(sih);  in si_chipid_fixup()  local
567 	ASSERT(sii->chipnew == 0);  in si_chipid_fixup()
570 			sii->chipnew = sih->chip; /* save it */  in si_chipid_fixup()
571 			sii->pub.chip = BCM43570_CHIP_ID; /* chip class */  in si_chipid_fixup()
576 			sii->chipnew = sih->chip; /* save it */  in si_chipid_fixup()
577 			sii->pub.chip = BCM43569_CHIP_ID; /* chip class */  in si_chipid_fixup()
581 			sii->chipnew = sih->chip; /* save it */  in si_chipid_fixup()
582 			sii->pub.chip = BCM4354_CHIP_ID; /* chip class */  in si_chipid_fixup()
586 			sii->chipnew = sih->chip; /* save it */  in si_chipid_fixup()
587 			sii->pub.chip = BCM4347_CHIP_ID; /* chip class */  in si_chipid_fixup()
591 			sii->chipnew = sih->chip; /* save it */  in si_chipid_fixup()
592 			sii->pub.chip = BCM4369_CHIP_ID; /* chip class */  in si_chipid_fixup()
687 si_doattach(si_info_t *sii, uint devid, osl_t *osh, volatile void *regs,  in si_doattach()  argument
690 	struct si_pub *sih = &sii->pub;  in si_doattach()
710 	sii->device_removed = FALSE;  in si_doattach()
712 	sii->curmap = regs;  in si_doattach()
713 	sii->sdh = sdh;  in si_doattach()
714 	sii->osh = osh;  in si_doattach()
715 	sii->second_bar0win = ~0x0;  in si_doattach()
732 	    (OSL_PCI_READ_CONFIG(sii->osh, PCI_SPROM_CONTROL, sizeof(uint32)) == 0xffffffff)) {  in si_doattach()
740 		savewin = OSL_PCI_READ_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32));  in si_doattach()
743 		OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, SI_ENUM_BASE(sih));  in si_doattach()
750 		cc = (chipcregs_t *)sii->curmap;  in si_doattach()
779 	if (!si_buscore_prep(sii, bustype, devid, sdh)) {  in si_doattach()
820 	if (CHIPTYPE(sii->pub.socitype) == SOCI_SB) {  in si_doattach()
822 		sb_scan(&sii->pub, regs, devid);  in si_doattach()
823 	} else if ((CHIPTYPE(sii->pub.socitype) == SOCI_AI) ||  in si_doattach()
824 		(CHIPTYPE(sii->pub.socitype) == SOCI_NAI) ||  in si_doattach()
825 		(CHIPTYPE(sii->pub.socitype) == SOCI_DVTBUS)) {  in si_doattach()
827 		if (CHIPTYPE(sii->pub.socitype) == SOCI_AI)  in si_doattach()
829 		else if (CHIPTYPE(sii->pub.socitype) == SOCI_NAI)  in si_doattach()
835 		if (sii->osh) {  in si_doattach()
836 			sii->axi_wrapper = (axi_wrapper_t *)MALLOCZ(sii->osh,  in si_doattach()
839 			if (sii->axi_wrapper == NULL) {  in si_doattach()
844 			sii->axi_wrapper = NULL;  in si_doattach()
847 		ai_scan(&sii->pub, (void *)(uintptr)cc, erombase,  devid);  in si_doattach()
848 	} else if (CHIPTYPE(sii->pub.socitype) == SOCI_UBUS) {  in si_doattach()
851 		ub_scan(&sii->pub, (void *)(uintptr)cc, devid);  in si_doattach()
857 	if (sii->numcores == 0) {  in si_doattach()
863 	if (!si_buscore_setup(sii, cc, bustype, savewin, &origidx, regs)) {  in si_doattach()
879 	if ((CCREV(sii->pub.ccrev) == 0x25) && ((CHIPID(sih->chip) == BCM43236_CHIP_ID ||  in si_doattach()
883 	                                 (CHIPREV(sii->pub.chiprev) <= 2))) {  in si_doattach()
950 	if (CHIP_HOSTIF_PCIE(&(sii->pub))) {  in si_doattach()
951 		uint32 sflags = si_arm_sflags(&(sii->pub));  in si_doattach()
969 		sii->lhl_ps_mode = LHL_PS_MODE_0;  in si_doattach()
974 		if (CCREV(sii->pub.ccrev) >= 20) {  in si_doattach()
994 	si_muxenab(sii, 3);  in si_doattach()
997 	return (sii);  in si_doattach()
1008 	si_info_t *sii = SI_INFO(sih);  in si_detach()  local
1009 	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;  in si_detach()
1022 		MFREE(sii->osh, cores_info, sizeof(si_cores_info_t));  in si_detach()
1026 		MFREE(sii->osh, sih->err_info, sizeof(si_axi_error_info_t));  in si_detach()
1027 		sii->pub.err_info = NULL;  in si_detach()
1031 	if (sii->axi_wrapper) {  in si_detach()
1032 		MFREE(sii->osh, sii->axi_wrapper,  in si_detach()
1034 		sii->axi_wrapper = NULL;  in si_detach()
1038 	if (sii != &ksii)  in si_detach()
1040 		MFREE(sii->osh, sii, sizeof(si_info_t));  in si_detach()
1046 	si_info_t *sii;  in si_osh()  local
1048 	sii = SI_INFO(sih);  in si_osh()
1049 	return sii->osh;  in si_osh()
1055 	si_info_t *sii;  in si_setosh()  local
1057 	sii = SI_INFO(sih);  in si_setosh()
1058 	if (sii->osh != NULL) {  in si_setosh()
1060 		ASSERT(!sii->osh);  in si_setosh()
1062 	sii->osh = osh;  in si_setosh()
1070 	si_info_t *sii = SI_INFO(sih);  in si_register_intr_callback()  local
1071 	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;  in si_register_intr_callback()
1072 	sii->intr_arg = intr_arg;  in si_register_intr_callback()
1073 	sii->intrsoff_fn = (si_intrsoff_t)intrsoff_fn;  in si_register_intr_callback()
1074 	sii->intrsrestore_fn = (si_intrsrestore_t)intrsrestore_fn;  in si_register_intr_callback()
1075 	sii->intrsenabled_fn = (si_intrsenabled_t)intrsenabled_fn;  in si_register_intr_callback()
1079 	sii->dev_coreid = cores_info->coreid[sii->curidx];  in si_register_intr_callback()
1085 	si_info_t *sii;  in si_deregister_intr_callback()  local
1087 	sii = SI_INFO(sih);  in si_deregister_intr_callback()
1088 	sii->intrsoff_fn = NULL;  in si_deregister_intr_callback()
1089 	sii->intrsrestore_fn = NULL;  in si_deregister_intr_callback()
1090 	sii->intrsenabled_fn = NULL;  in si_deregister_intr_callback()
1096 	si_info_t *sii = SI_INFO(sih);  in si_intflag()  local
1103 		return R_REG(sii->osh, ((uint32 *)(uintptr)  in si_intflag()
1104 			    (sii->oob_router + OOB_STATUSA)));  in si_intflag()
1159 	si_info_t *sii = SI_INFO(sih);  in si_oobr_baseaddr()  local
1166 		return (second ? sii->oob_router1 : sii->oob_router);  in si_oobr_baseaddr()
1176 	si_info_t *sii = SI_INFO(sih);  in si_coreid()  local
1177 	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;  in si_coreid()
1179 	return cores_info->coreid[sii->curidx];  in si_coreid()
1185 	si_info_t *sii;  in si_coreidx()  local
1187 	sii = SI_INFO(sih);  in si_coreidx()
1188 	return sii->curidx;  in si_coreidx()
1201 	si_info_t *sii = SI_INFO(sih);  in si_coreunit()  local
1202 	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;  in si_coreunit()
1210 	idx = sii->curidx;  in si_coreunit()
1212 	ASSERT(GOODREGS(sii->curmap));  in si_coreunit()
1277 	si_info_t *sii = SI_INFO(sih);  in si_findcoreidx()  local
1278 	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;  in si_findcoreidx()
1284 	for (i = 0; i < sii->numcores; i++)  in si_findcoreidx()
1298 	si_info_t *sii = SI_INFO(sih);  in si_numcoreunits()  local
1299 	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;  in si_numcoreunits()
1303 	for (i = 0; i < sii->numcores; i++) {  in si_numcoreunits()
1335 	si_info_t *sii = SI_INFO(sih);  in si_corelist()  local
1336 	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;  in si_corelist()
1338 	bcopy((uchar*)cores_info->coreid, (uchar*)coreid, (sii->numcores * sizeof(uint)));  in si_corelist()
1339 	return (sii->numcores);  in si_corelist()
1346 	si_info_t *sii;  in si_wrapperregs()  local
1348 	sii = SI_INFO(sih);  in si_wrapperregs()
1349 	ASSERT(GOODREGS(sii->curwrap));  in si_wrapperregs()
1351 	return (sii->curwrap);  in si_wrapperregs()
1358 	si_info_t *sii;  in si_coreregs()  local
1360 	sii = SI_INFO(sih);  in si_coreregs()
1361 	ASSERT(GOODREGS(sii->curmap));  in si_coreregs()
1363 	return (sii->curmap);  in si_coreregs()
1416 	si_info_t *sii = SI_INFO(sih);  in si_switch_core()  local
1418 	if (SI_FAST(sii)) {  in si_switch_core()
1425 			return (volatile void *)CCREGS_FAST(sii);  in si_switch_core()
1427 			return (volatile void *)PCIEREGS(sii);  in si_switch_core()
1429 	INTR_OFF(sii, *intr_val);  in si_switch_core()
1430 	*origidx = sii->curidx;  in si_switch_core()
1441 	si_info_t *sii = SI_INFO(sih);  in si_restore_core()  local
1443 	if (SI_FAST(sii) && ((coreid == CC_CORE_ID) || (coreid == BUSCORETYPE(sih->buscoretype))))  in si_restore_core()
1447 	INTR_RESTORE(sii, intr_val);  in si_restore_core()
1653 	si_info_t *sii = SI_INFO(sih);  in si_invalidate_second_bar0win()  local
1654 	sii->second_bar0win = ~0x0;  in si_invalidate_second_bar0win()
1662 	si_info_t *sii = SI_INFO(sih);  in si_backplane_access()  local
1679 	if (sii->second_bar0win != region) {  in si_backplane_access()
1680 		OSL_PCI_WRITE_CONFIG(sii->osh, PCIE2_BAR0_CORE2_WIN, 4, region);  in si_backplane_access()
1681 		sii->second_bar0win = region;  in si_backplane_access()
1689 	r = (volatile uint32 *)((volatile char *)sii->curmap + PCI_SECOND_BAR0_OFFSET + addr);  in si_backplane_access()
1692 		(volatile char*)sii->curmap, region, addr, r, read));  in si_backplane_access()
1697 				*val = R_REG(sii->osh, (volatile uint8*)r);  in si_backplane_access()
1699 				W_REG(sii->osh, (volatile uint8*)r, *val);  in si_backplane_access()
1703 				*val = R_REG(sii->osh, (volatile uint16*)r);  in si_backplane_access()
1705 				W_REG(sii->osh, (volatile uint16*)r, *val);  in si_backplane_access()
1709 				*val = R_REG(sii->osh, (volatile uint32*)r);  in si_backplane_access()
1711 				W_REG(sii->osh, (volatile uint32*)r, *val);  in si_backplane_access()
1867 	si_info_t *sii = SI_INFO(sih);  in si_get_slaveport_addr()  local
1868 	uint origidx = sii->curidx;  in si_get_slaveport_addr()
1889 	si_info_t *sii = SI_INFO(sih);  in si_get_d11_slaveport_addr()  local
1890 	uint origidx = sii->curidx;  in si_get_d11_slaveport_addr()
2200 si_slowclk_src(si_info_t *sii)  in si_slowclk_src()  argument
2204 	ASSERT(SI_FAST(sii) || si_coreid(&sii->pub) == CC_CORE_ID);  in si_slowclk_src()
2206 	if (CCREV(sii->pub.ccrev) < 6) {  in si_slowclk_src()
2207 		if ((BUSTYPE(sii->pub.bustype) == PCI_BUS) &&  in si_slowclk_src()
2208 		    (OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUT, sizeof(uint32)) &  in si_slowclk_src()
2213 	} else if (CCREV(sii->pub.ccrev) < 10) {  in si_slowclk_src()
2214 		cc = (chipcregs_t *)si_setcoreidx(&sii->pub, sii->curidx);  in si_slowclk_src()
2216 		return (R_REG(sii->osh, &cc->slow_clk_ctl) & SCC_SS_MASK);  in si_slowclk_src()
2223 si_slowclk_freq(si_info_t *sii, bool max_freq, chipcregs_t *cc)  in si_slowclk_freq()  argument
2228 	ASSERT(SI_FAST(sii) || si_coreid(&sii->pub) == CC_CORE_ID);  in si_slowclk_freq()
2231 	ASSERT(R_REG(sii->osh, &cc->capabilities) & CC_CAP_PWR_CTL);  in si_slowclk_freq()
2233 	slowclk = si_slowclk_src(sii);  in si_slowclk_freq()
2234 	if (CCREV(sii->pub.ccrev) < 6) {  in si_slowclk_freq()
2239 	} else if (CCREV(sii->pub.ccrev) < 10) {  in si_slowclk_freq()
2241 		        (((R_REG(sii->osh, &cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);  in si_slowclk_freq()
2252 		div = R_REG(sii->osh, &cc->system_clk_ctl) >> SYCC_CD_SHIFT;  in si_slowclk_freq()
2260 si_clkctl_setdelay(si_info_t *sii, void *chipcregs)  in si_clkctl_setdelay()  argument
2272 	slowclk = si_slowclk_src(sii);  in si_clkctl_setdelay()
2277 	slowmaxfreq = si_slowclk_freq(sii, (CCREV(sii->pub.ccrev) >= 10) ? FALSE : TRUE, cc);  in si_clkctl_setdelay()
2282 	W_REG(sii->osh, &cc->pll_on_delay, pll_on_delay);  in si_clkctl_setdelay()
2283 	W_REG(sii->osh, &cc->fref_sel_delay, fref_sel_delay);  in si_clkctl_setdelay()
2290 	si_info_t *sii;  in si_clkctl_init()  local
2298 	sii = SI_INFO(sih);  in si_clkctl_init()
2299 	fast = SI_FAST(sii);  in si_clkctl_init()
2301 		origidx = sii->curidx;  in si_clkctl_init()
2304 	} else if ((cc = (chipcregs_t *)CCREGS_FAST(sii)) == NULL)  in si_clkctl_init()
2310 		SET_REG(sii->osh, &cc->system_clk_ctl, SYCC_CD_MASK,  in si_clkctl_init()
2313 	si_clkctl_setdelay(sii, (void *)(uintptr)cc);  in si_clkctl_init()
2583 sysmem_banksize(si_info_t *sii, sysmemregs_t *regs, uint8 idx)  in sysmem_banksize()  argument
2588 	W_REG(sii->osh, &regs->bankidx, bankidx);  in sysmem_banksize()
2589 	bankinfo = R_REG(sii->osh, &regs->bankinfo);  in sysmem_banksize()
2598 	si_info_t *sii = SI_INFO(sih);  in si_sysmem_size()  local
2610 	INTR_OFF(sii, intr_val);  in si_sysmem_size()
2620 	coreinfo = R_REG(sii->osh, &regs->coreinfo);  in si_sysmem_size()
2627 		memsize += sysmem_banksize(sii, regs, i + nrb);  in si_sysmem_size()
2632 	INTR_RESTORE(sii, intr_val);  in si_sysmem_size()
2639 socram_banksize(si_info_t *sii, sbsocramregs_t *regs, uint8 idx, uint8 mem_type)  in socram_banksize()  argument
2646 	W_REG(sii->osh, &regs->bankidx, bankidx);  in socram_banksize()
2647 	bankinfo = R_REG(sii->osh, &regs->bankinfo);  in socram_banksize()
2654 	si_info_t *sii = SI_INFO(sih);  in si_socram_set_bankpda()  local
2662 	INTR_OFF(sii, intr_val);  in si_socram_set_bankpda()
2674 		W_REG(sii->osh, &regs->bankidx, bankidx);  in si_socram_set_bankpda()
2675 		W_REG(sii->osh, &regs->bankpda, bankpda);  in si_socram_set_bankpda()
2684 	INTR_RESTORE(sii, intr_val);  in si_socram_set_bankpda()
2690 	si_info_t *sii = SI_INFO(sih);  in si_socdevram()  local
2698 	INTR_OFF(sii, intr_val);  in si_socdevram()
2719 		extcinfo = R_REG(sii->osh, &regs->extracoreinfo);  in si_socdevram()
2723 			W_REG(sii->osh, &regs->bankidx, bankidx);  in si_socdevram()
2724 			bankinfo = R_REG(sii->osh, &regs->bankinfo);  in si_socdevram()
2737 				W_REG(sii->osh, &regs->bankinfo, bankinfo);  in si_socdevram()
2756 	INTR_RESTORE(sii, intr_val);  in si_socdevram()
2762 	si_info_t *sii = SI_INFO(sih);  in si_socdevram_remap_isenb()  local
2774 	INTR_OFF(sii, intr_val);  in si_socdevram_remap_isenb()
2787 		extcinfo = R_REG(sii->osh, &regs->extracoreinfo);  in si_socdevram_remap_isenb()
2791 			W_REG(sii->osh, &regs->bankidx, bankidx);  in si_socdevram_remap_isenb()
2792 			bankinfo = R_REG(sii->osh, &regs->bankinfo);  in si_socdevram_remap_isenb()
2806 	INTR_RESTORE(sii, intr_val);  in si_socdevram_remap_isenb()
2822 	si_info_t *sii = SI_INFO(sih);  in si_socdevram_size()  local
2831 	INTR_OFF(sii, intr_val);  in si_socdevram_size()
2848 		extcinfo = R_REG(sii->osh, &regs->extracoreinfo);  in si_socdevram_size()
2851 			memsize += socram_banksize(sii, regs, i, SOCRAM_MEMTYPE_DEVRAM);  in si_socdevram_size()
2860 	INTR_RESTORE(sii, intr_val);  in si_socdevram_size()
2868 	si_info_t *sii = SI_INFO(sih);  in si_socdevram_remap_size()  local
2881 	INTR_OFF(sii, intr_val);  in si_socdevram_remap_size()
2894 		extcinfo = R_REG(sii->osh, &regs->extracoreinfo);  in si_socdevram_remap_size()
2906 			W_REG(sii->osh, &regs->bankidx, bankidx);  in si_socdevram_remap_size()
2907 			bankinfo = R_REG(sii->osh, &regs->bankinfo);  in si_socdevram_remap_size()
2909 				banksz = socram_banksize(sii, regs, i, SOCRAM_MEMTYPE_DEVRAM);  in si_socdevram_remap_size()
2924 	INTR_RESTORE(sii, intr_val);  in si_socdevram_remap_size()
2933 	si_info_t *sii = SI_INFO(sih);  in si_socram_size()  local
2944 	INTR_OFF(sii, intr_val);  in si_socram_size()
2955 	coreinfo = R_REG(sii->osh, &regs->coreinfo);  in si_socram_size()
2982 			memsize += socram_banksize(sii, regs, i, SOCRAM_MEMTYPE_RAM);  in si_socram_size()
2991 	INTR_RESTORE(sii, intr_val);  in si_socram_size()
3000 	si_info_t *sii = SI_INFO(sih);  in si_tcm_size()  local
3018 	INTR_OFF(sii, intr_val);  in si_tcm_size()
3034 	corecap = R_REG(sii->osh, arm_cap_reg);  in si_tcm_size()
3043 		W_REG(sii->osh, arm_bidx, idx);  in si_tcm_size()
3045 		bxinfo = R_REG(sii->osh, arm_binfo);  in si_tcm_size()
3062 	INTR_RESTORE(sii, intr_val);  in si_tcm_size()
3087 	si_info_t *sii = SI_INFO(sih);  in si_socram_srmem_size()  local
3103 	INTR_OFF(sii, intr_val);  in si_socram_srmem_size()
3114 	coreinfo = R_REG(sii->osh, &regs->coreinfo);  in si_socram_srmem_size()
3121 			W_REG(sii->osh, &regs->bankidx, i);  in si_socram_srmem_size()
3122 			if (R_REG(sii->osh, &regs->bankinfo) & SOCRAM_BANKINFO_RETNTRAM_MASK)  in si_socram_srmem_size()
3123 				memsize += socram_banksize(sii, regs, i, SOCRAM_MEMTYPE_RAM);  in si_socram_srmem_size()
3133 	INTR_RESTORE(sii, intr_val);  in si_socram_srmem_size()
3142 	si_info_t *sii = SI_INFO(sih);  in si_btcgpiowar()  local
3154 	INTR_OFF(sii, intr_val);  in si_btcgpiowar()
3161 	W_REG(sii->osh, &cc->uart0mcr, R_REG(sii->osh, &cc->uart0mcr) | 0x04);  in si_btcgpiowar()
3166 	INTR_RESTORE(sii, intr_val);  in si_btcgpiowar()
3172 	si_info_t *sii = SI_INFO(sih);  in si_chipcontrl_restore()  local
3180 	W_REG(sii->osh, &cc->chipcontrol, val);  in si_chipcontrl_restore()
3187 	si_info_t *sii = SI_INFO(sih);  in si_chipcontrl_read()  local
3196 	val = R_REG(sii->osh, &cc->chipcontrol);  in si_chipcontrl_read()
3205 	si_info_t *sii = SI_INFO(sih);  in si_chipcontrl_srom4360()  local
3214 	val = R_REG(sii->osh, &cc->chipcontrol);  in si_chipcontrl_srom4360()
3223 		W_REG(sii->osh, &cc->chipcontrol, val);  in si_chipcontrl_srom4360()
3237 	si_info_t *sii = SI_INFO(sih);  in si_srom_clk_set()  local
3248 	val = R_REG(sii->osh, &cc->clkdiv2);  in si_srom_clk_set()
3255 	W_REG(sii->osh, &cc->clkdiv2, ((val & ~CLKD2_SROM) | divisor));  in si_srom_clk_set()
3268 	si_info_t *sii = SI_INFO(sih);  in si_btc_enable_chipcontrol()  local
3278 	W_REG(sii->osh, &cc->chipcontrol,  in si_btc_enable_chipcontrol()
3279 		R_REG(sii->osh, &cc->chipcontrol) | CC_BTCOEX_EN_MASK);  in si_btc_enable_chipcontrol()
3287 	si_info_t *sii = SI_INFO(sih);  in si_set_device_removed()  local
3289 	sii->device_removed = status;  in si_set_device_removed()
3297 	si_info_t *sii = SI_INFO(sih);  in si_deviceremoved()  local
3299 	if (sii->device_removed) {  in si_deviceremoved()
3329 		si_info_t *sii;  in si_is_sprom_available()  local
3337 		sii = SI_INFO(sih);  in si_is_sprom_available()
3338 		origidx = sii->curidx;  in si_is_sprom_available()
3341 		sromctrl = R_REG(sii->osh, &cc->sromcontrol);  in si_is_sprom_available()
3451 	si_info_t *sii = SI_INFO(sih);  in si_core_wrapperreg()  local
3455 	INTR_OFF(sii, intr_val);  in si_core_wrapperreg()
3462 	INTR_RESTORE(sii, intr_val);  in si_core_wrapperreg()
3582 		si_info_t *sii = SI_INFO(sih);  in si_slave_wrapper_add()  local
3584 		int wrapper_idx = (int)sii->axi_num_wrappers - 1;  in si_slave_wrapper_add()
3588 			if (sii->axi_wrapper[wrapper_idx].wrapper_type == AI_SLAVE_WRAPPER &&  in si_slave_wrapper_add()
3589 				sii->axi_wrapper[wrapper_idx].cid == 0xfff) {  in si_slave_wrapper_add()
3590 				sii->axi_wrapper[wrapper_idx].wrapper_addr = 0x1810b000;  in si_slave_wrapper_add()
3688 	si_info_t *sii = SI_INFO(sih);  in si_corereg_pciefast_write()  local
3692 	r = (volatile uint32 *)((volatile char *)sii->curmap +  in si_corereg_pciefast_write()
3695 	W_REG(sii->osh, r, val);  in si_corereg_pciefast_write()
3702 	si_info_t *sii = SI_INFO(sih);  in si_corereg_pciefast_read()  local
3706 	r = (volatile uint32 *)((volatile char *)sii->curmap +  in si_corereg_pciefast_read()
3709 	return R_REG(sii->osh, r);  in si_corereg_pciefast_read()
3854 	si_info_t *sii = SI_INFO(sih);  in si_raw_reg()  local
3860 	if (sii == NULL) {  in si_raw_reg()
3874 	if (PCIE_GEN2(sii)) {  in si_raw_reg()
3878 		addr = (volatile uint32*)(((volatile uint8*)sii->curmap) +  in si_raw_reg()
3886 		addr = (volatile uint32*)(((volatile uint8*)sii->curmap) +  in si_raw_reg()
3891 	prev_value = OSL_PCI_READ_CONFIG(sii->osh, cfg_reg, 4);  in si_raw_reg()
3894 		OSL_PCI_WRITE_CONFIG(sii->osh, cfg_reg,  in si_raw_reg()
3902 		W_REG(sii->osh, addr, val);  in si_raw_reg()
3904 		val = R_REG(sii->osh, addr);  in si_raw_reg()
3909 		OSL_PCI_WRITE_CONFIG(sii->osh,  in si_raw_reg()
3919 	si_info_t *sii = SI_INFO(sih);  in si_lhl_ps_mode()  local
3920 	return sii->lhl_ps_mode;  in si_lhl_ps_mode()