Lines Matching refs:sih
342 si_get_pmu_reg_addr(si_t *sih, uint32 offset) in si_get_pmu_reg_addr() argument
344 si_info_t *sii = SI_INFO(sih); in si_get_pmu_reg_addr()
360 si_setcoreidx(sih, origidx); in si_get_pmu_reg_addr()
362 pmuaddr = SI_ENUM_BASE(sih) + offset; in si_get_pmu_reg_addr()
377 struct si_pub *sih = &sii->pub; in si_buscore_setup() local
400 if (!sih->chipidpresent) { in si_buscore_setup()
412 struct si_pub *sih = &sii->pub; in si_buscore_setup() local
424 sii->pub.gcirev = si_corereg(sih, GCI_CORE_IDX(sih), in si_buscore_setup()
425 GCI_OFFSETOF(sih, gci_corecaps0), 0, 0) & in si_buscore_setup()
554 si_chipid(si_t *sih) in si_chipid() argument
556 si_info_t *sii = SI_INFO(sih); in si_chipid()
558 return (sii->chipnew) ? sii->chipnew : sih->chip; in si_chipid()
563 si_chipid_fixup(si_t *sih) in si_chipid_fixup() argument
565 si_info_t *sii = SI_INFO(sih); in si_chipid_fixup()
568 switch (sih->chip) { in si_chipid_fixup()
570 sii->chipnew = sih->chip; /* save it */ in si_chipid_fixup()
576 sii->chipnew = sih->chip; /* save it */ in si_chipid_fixup()
581 sii->chipnew = sih->chip; /* save it */ in si_chipid_fixup()
586 sii->chipnew = sih->chip; /* save it */ in si_chipid_fixup()
591 sii->chipnew = sih->chip; /* save it */ in si_chipid_fixup()
602 si_check_boot_type(si_t *sih, osl_t *osh) in si_check_boot_type() argument
604 if (sih->pmurev >= 30) { in si_check_boot_type()
605 boot_type = PMU_REG_NEW(sih, swscratch, 0, 0); in si_check_boot_type()
607 boot_type = CHIPC_REG(sih, flashdata, 0, 0); in si_check_boot_type()
616 si_clear_backplane_to_fast(void *sih, void *addr) in si_clear_backplane_to_fast() argument
618 si_t *_sih = DISCARD_QUAL(sih, si_t); in si_clear_backplane_to_fast()
628 si_get_axi_errlog_info(si_t *sih) in si_get_axi_errlog_info() argument
630 if (CHIPTYPE(sih->socitype) == SOCI_AI) { in si_get_axi_errlog_info()
631 return (const si_axi_error_info_t *)sih->err_info; in si_get_axi_errlog_info()
638 si_reset_axi_errlog_info(si_t *sih) in si_reset_axi_errlog_info() argument
640 if (sih->err_info) { in si_reset_axi_errlog_info()
641 sih->err_info->count = 0; in si_reset_axi_errlog_info()
690 struct si_pub *sih = &sii->pub; in si_doattach() local
709 sih->buscoreidx = BADIDX; in si_doattach()
716 sih->enum_base = si_enum_base(devid); in si_doattach()
719 sih->err_info = MALLOCZ(osh, sizeof(si_axi_error_info_t)); in si_doattach()
720 if (sih->err_info == NULL) { in si_doattach()
727 osl_set_bpt_cb(osh, (void *)si_clear_backplane_to_fast, (void *)sih); in si_doattach()
741 if (!GOODCOREADDR(savewin, SI_ENUM_BASE(sih))) in si_doattach()
742 savewin = SI_ENUM_BASE(sih); in si_doattach()
743 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, SI_ENUM_BASE(sih)); in si_doattach()
753 sih->chipidpresent = TRUE; in si_doattach()
761 sih->secureboot = TRUE; in si_doattach()
765 cc = (chipcregs_t *)REG_MAP(SI_ENUM_BASE(sih), SI_CORE_SIZE); in si_doattach()
769 sih->bustype = bustype; in si_doattach()
796 sih->socitype = (w & CID_TYPE_MASK) >> CID_TYPE_SHIFT; in si_doattach()
798 sih->chip = w & CID_ID_MASK; in si_doattach()
799 sih->chiprev = (w & CID_REV_MASK) >> CID_REV_SHIFT; in si_doattach()
800 sih->chippkg = (w & CID_PKG_MASK) >> CID_PKG_SHIFT; in si_doattach()
802 si_chipid_fixup(sih); in si_doattach()
804 if (CHIPID(sih->chip) == BCM43465_CHIP_ID) { in si_doattach()
805 sih->chip = BCM4366_CHIP_ID; in si_doattach()
806 } else if (CHIPID(sih->chip) == BCM43525_CHIP_ID) { in si_doattach()
807 sih->chip = BCM4365_CHIP_ID; in si_doattach()
810 sih->issim = IS_SIM(sih->chippkg); in si_doattach()
813 if (MULTIBP_CAP(sih)) in si_doattach()
815 sih->_multibp_enable = TRUE; in si_doattach()
849 SI_MSG(("Found chip type UBUS (0x%08x), chip id = 0x%4x\n", w, sih->chip)); in si_doattach()
869 si_check_boot_type(sih, osh); in si_doattach()
870 if (ulp_module_init(osh, sih) != BCME_OK) { in si_doattach()
879 if ((CCREV(sii->pub.ccrev) == 0x25) && ((CHIPID(sih->chip) == BCM43236_CHIP_ID || in si_doattach()
880 CHIPID(sih->chip) == BCM43235_CHIP_ID || in si_doattach()
881 CHIPID(sih->chip) == BCM43234_CHIP_ID || in si_doattach()
882 CHIPID(sih->chip) == BCM43238_CHIP_ID) && in si_doattach()
923 if ((CHIPID(sih->chip) == BCM43131_CHIP_ID) || in si_doattach()
924 (CHIPID(sih->chip) == BCM43217_CHIP_ID)) { in si_doattach()
930 savecore = si_coreidx(sih); in si_doattach()
931 si_setcore(sih, CC_CORE_ID, 0); in si_doattach()
938 si_setcoreidx(sih, savecore); in si_doattach()
959 hnd_cpu_wait(sih); in si_doattach()
976 cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0); in si_doattach()
980 si_setcoreidx(sih, origidx); in si_doattach()
986 ASSERT(!si_taclear(sih, FALSE)); in si_doattach()
989 si_pmustatstimer_init(sih); in si_doattach()
1006 si_detach(si_t *sih) in si_detach() argument
1008 si_info_t *sii = SI_INFO(sih); in si_detach()
1012 if (BUSTYPE(sih->bustype) == SI_BUS) in si_detach()
1025 if (sih->err_info) { in si_detach()
1026 MFREE(sii->osh, sih->err_info, sizeof(si_axi_error_info_t)); in si_detach()
1044 si_osh(si_t *sih) in si_osh() argument
1048 sii = SI_INFO(sih); in si_osh()
1053 si_setosh(si_t *sih, osl_t *osh) in si_setosh() argument
1057 sii = SI_INFO(sih); in si_setosh()
1067 si_register_intr_callback(si_t *sih, void *intrsoff_fn, void *intrsrestore_fn, in si_register_intr_callback() argument
1070 si_info_t *sii = SI_INFO(sih); in si_register_intr_callback()
1083 si_deregister_intr_callback(si_t *sih) in si_deregister_intr_callback() argument
1087 sii = SI_INFO(sih); in si_deregister_intr_callback()
1094 si_intflag(si_t *sih) in si_intflag() argument
1096 si_info_t *sii = SI_INFO(sih); in si_intflag()
1098 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_intflag()
1099 return sb_intflag(sih); in si_intflag()
1100 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_intflag()
1101 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_intflag()
1102 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_intflag()
1112 si_flag(si_t *sih) in si_flag() argument
1114 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_flag()
1115 return sb_flag(sih); in si_flag()
1116 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_flag()
1117 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_flag()
1118 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_flag()
1119 return ai_flag(sih); in si_flag()
1120 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in si_flag()
1121 return ub_flag(sih); in si_flag()
1129 si_flag_alt(si_t *sih) in si_flag_alt() argument
1131 if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_flag_alt()
1132 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_flag_alt()
1133 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_flag_alt()
1134 return ai_flag_alt(sih); in si_flag_alt()
1142 si_setint(si_t *sih, int siflag) in si_setint() argument
1144 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_setint()
1145 sb_setint(sih, siflag); in si_setint()
1146 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_setint()
1147 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_setint()
1148 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_setint()
1149 ai_setint(sih, siflag); in si_setint()
1150 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in si_setint()
1151 ub_setint(sih, siflag); in si_setint()
1157 si_oobr_baseaddr(si_t *sih, bool second) in si_oobr_baseaddr() argument
1159 si_info_t *sii = SI_INFO(sih); in si_oobr_baseaddr()
1161 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_oobr_baseaddr()
1163 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_oobr_baseaddr()
1164 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_oobr_baseaddr()
1165 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_oobr_baseaddr()
1174 si_coreid(si_t *sih) in si_coreid() argument
1176 si_info_t *sii = SI_INFO(sih); in si_coreid()
1183 si_coreidx(si_t *sih) in si_coreidx() argument
1187 sii = SI_INFO(sih); in si_coreidx()
1192 si_d11_switch_addrbase(si_t *sih, uint coreunit) in si_d11_switch_addrbase() argument
1194 return si_setcore(sih, D11_CORE_ID, coreunit); in si_d11_switch_addrbase()
1199 si_coreunit(si_t *sih) in si_coreunit() argument
1201 si_info_t *sii = SI_INFO(sih); in si_coreunit()
1213 coreid = si_coreid(sih); in si_coreunit()
1224 si_corevendor(si_t *sih) in si_corevendor() argument
1226 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_corevendor()
1227 return sb_corevendor(sih); in si_corevendor()
1228 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_corevendor()
1229 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_corevendor()
1230 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_corevendor()
1231 return ai_corevendor(sih); in si_corevendor()
1232 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in si_corevendor()
1233 return ub_corevendor(sih); in si_corevendor()
1241 si_backplane64(si_t *sih) in si_backplane64() argument
1243 return ((sih->cccaps & CC_CAP_BKPLN64) != 0); in si_backplane64()
1247 si_corerev(si_t *sih) in si_corerev() argument
1249 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_corerev()
1250 return sb_corerev(sih); in si_corerev()
1251 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_corerev()
1252 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_corerev()
1253 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_corerev()
1254 return ai_corerev(sih); in si_corerev()
1255 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in si_corerev()
1256 return ub_corerev(sih); in si_corerev()
1264 si_corerev_minor(si_t *sih) in si_corerev_minor() argument
1266 if (CHIPTYPE(sih->socitype) == SOCI_AI) { in si_corerev_minor()
1267 return ai_corerev_minor(sih); in si_corerev_minor()
1275 si_findcoreidx(si_t *sih, uint coreid, uint coreunit) in si_findcoreidx() argument
1277 si_info_t *sii = SI_INFO(sih); in si_findcoreidx()
1296 si_numcoreunits(si_t *sih, uint coreid) in si_numcoreunits() argument
1298 si_info_t *sii = SI_INFO(sih); in si_numcoreunits()
1314 BCMRAMFN(si_numd11coreunits)(si_t *sih) in BCMRAMFN()
1318 found = si_numcoreunits(sih, D11_CORE_ID); in BCMRAMFN()
1333 si_corelist(si_t *sih, uint coreid[]) in si_corelist() argument
1335 si_info_t *sii = SI_INFO(sih); in si_corelist()
1344 si_wrapperregs(si_t *sih) in si_wrapperregs() argument
1348 sii = SI_INFO(sih); in si_wrapperregs()
1356 si_coreregs(si_t *sih) in si_coreregs() argument
1360 sii = SI_INFO(sih); in si_coreregs()
1372 si_setcore(si_t *sih, uint coreid, uint coreunit) in si_setcore() argument
1376 idx = si_findcoreidx(sih, coreid, coreunit); in si_setcore()
1380 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_setcore()
1381 return sb_setcoreidx(sih, idx); in si_setcore()
1382 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_setcore()
1383 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_setcore()
1384 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_setcore()
1385 return ai_setcoreidx(sih, idx); in si_setcore()
1386 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in si_setcore()
1387 return ub_setcoreidx(sih, idx); in si_setcore()
1395 si_setcoreidx(si_t *sih, uint coreidx) in si_setcoreidx() argument
1397 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_setcoreidx()
1398 return sb_setcoreidx(sih, coreidx); in si_setcoreidx()
1399 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_setcoreidx()
1400 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_setcoreidx()
1401 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_setcoreidx()
1402 return ai_setcoreidx(sih, coreidx); in si_setcoreidx()
1403 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in si_setcoreidx()
1404 return ub_setcoreidx(sih, coreidx); in si_setcoreidx()
1413 si_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val) in si_switch_core() argument
1416 si_info_t *sii = SI_INFO(sih); in si_switch_core()
1426 else if (coreid == BUSCORETYPE(sih->buscoretype)) in si_switch_core()
1431 cc = si_setcore(sih, coreid, 0); in si_switch_core()
1439 si_restore_core(si_t *sih, uint coreid, uint intr_val) in si_restore_core() argument
1441 si_info_t *sii = SI_INFO(sih); in si_restore_core()
1443 if (SI_FAST(sii) && ((coreid == CC_CORE_ID) || (coreid == BUSCORETYPE(sih->buscoretype)))) in si_restore_core()
1446 si_setcoreidx(sih, coreid); in si_restore_core()
1451 si_numaddrspaces(si_t *sih) in si_numaddrspaces() argument
1453 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_numaddrspaces()
1454 return sb_numaddrspaces(sih); in si_numaddrspaces()
1455 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_numaddrspaces()
1456 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_numaddrspaces()
1457 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_numaddrspaces()
1458 return ai_numaddrspaces(sih); in si_numaddrspaces()
1459 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in si_numaddrspaces()
1460 return ub_numaddrspaces(sih); in si_numaddrspaces()
1475 si_addrspace(si_t *sih, uint spidx, uint baidx) in si_addrspace() argument
1477 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_addrspace()
1478 return sb_addrspace(sih, baidx); in si_addrspace()
1479 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_addrspace()
1480 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_addrspace()
1481 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_addrspace()
1482 return ai_addrspace(sih, spidx, baidx); in si_addrspace()
1483 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in si_addrspace()
1484 return ub_addrspace(sih, baidx); in si_addrspace()
1498 si_addrspacesize(si_t *sih, uint spidx, uint baidx) in si_addrspacesize() argument
1500 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_addrspacesize()
1501 return sb_addrspacesize(sih, baidx); in si_addrspacesize()
1502 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_addrspacesize()
1503 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_addrspacesize()
1504 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_addrspacesize()
1505 return ai_addrspacesize(sih, spidx, baidx); in si_addrspacesize()
1506 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in si_addrspacesize()
1507 return ub_addrspacesize(sih, baidx); in si_addrspacesize()
1515 si_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, uint32 *size) in si_coreaddrspaceX() argument
1518 if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_coreaddrspaceX()
1519 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_coreaddrspaceX()
1520 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_coreaddrspaceX()
1521 ai_coreaddrspaceX(sih, asidx, addr, size); in si_coreaddrspaceX()
1527 si_core_cflags(si_t *sih, uint32 mask, uint32 val) in si_core_cflags() argument
1529 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_core_cflags()
1530 return sb_core_cflags(sih, mask, val); in si_core_cflags()
1531 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_core_cflags()
1532 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_core_cflags()
1533 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_core_cflags()
1534 return ai_core_cflags(sih, mask, val); in si_core_cflags()
1535 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in si_core_cflags()
1536 return ub_core_cflags(sih, mask, val); in si_core_cflags()
1544 si_core_cflags_wo(si_t *sih, uint32 mask, uint32 val) in si_core_cflags_wo() argument
1546 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_core_cflags_wo()
1547 sb_core_cflags_wo(sih, mask, val); in si_core_cflags_wo()
1548 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_core_cflags_wo()
1549 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_core_cflags_wo()
1550 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_core_cflags_wo()
1551 ai_core_cflags_wo(sih, mask, val); in si_core_cflags_wo()
1552 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in si_core_cflags_wo()
1553 ub_core_cflags_wo(sih, mask, val); in si_core_cflags_wo()
1559 si_core_sflags(si_t *sih, uint32 mask, uint32 val) in si_core_sflags() argument
1561 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_core_sflags()
1562 return sb_core_sflags(sih, mask, val); in si_core_sflags()
1563 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_core_sflags()
1564 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_core_sflags()
1565 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_core_sflags()
1566 return ai_core_sflags(sih, mask, val); in si_core_sflags()
1567 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in si_core_sflags()
1568 return ub_core_sflags(sih, mask, val); in si_core_sflags()
1576 si_commit(si_t *sih) in si_commit() argument
1578 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_commit()
1579 sb_commit(sih); in si_commit()
1580 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_commit()
1581 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_commit()
1582 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_commit()
1584 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in si_commit()
1592 si_iscoreup(si_t *sih) in si_iscoreup() argument
1594 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_iscoreup()
1595 return sb_iscoreup(sih); in si_iscoreup()
1596 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_iscoreup()
1597 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_iscoreup()
1598 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_iscoreup()
1599 return ai_iscoreup(sih); in si_iscoreup()
1600 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in si_iscoreup()
1601 return ub_iscoreup(sih); in si_iscoreup()
1609 si_wrapperreg(si_t *sih, uint32 offset, uint32 mask, uint32 val) in si_wrapperreg() argument
1612 if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_wrapperreg()
1613 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_wrapperreg()
1614 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_wrapperreg()
1615 return (ai_wrap_reg(sih, offset, mask, val)); in si_wrapperreg()
1651 si_invalidate_second_bar0win(si_t *sih) in si_invalidate_second_bar0win() argument
1653 si_info_t *sii = SI_INFO(sih); in si_invalidate_second_bar0win()
1658 si_backplane_access(si_t *sih, uint addr, uint size, uint *val, bool read) in si_backplane_access() argument
1662 si_info_t *sii = SI_INFO(sih); in si_backplane_access()
1665 if (BUSTYPE(sih->bustype) != PCI_BUS) { in si_backplane_access()
1722 si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val) in si_corereg() argument
1724 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_corereg()
1725 return sb_corereg(sih, coreidx, regoff, mask, val); in si_corereg()
1726 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_corereg()
1727 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_corereg()
1728 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_corereg()
1729 return ai_corereg(sih, coreidx, regoff, mask, val); in si_corereg()
1730 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in si_corereg()
1731 return ub_corereg(sih, coreidx, regoff, mask, val); in si_corereg()
1739 si_corereg_writeonly(si_t *sih, uint coreidx, uint regoff, uint mask, uint val) in si_corereg_writeonly() argument
1741 return ai_corereg_writeonly(sih, coreidx, regoff, mask, val); in si_corereg_writeonly()
1759 si_pmu_corereg(si_t *sih, uint32 idx, uint regoff, uint mask, uint val) in si_pmu_corereg() argument
1764 if (mask != 0 && PMUREV(sih->pmurev) >= 22 && in si_pmu_corereg()
1766 pmustatus_offset = AOB_ENAB(sih) ? OFFSETOF(pmuregs_t, pmustatus) : in si_pmu_corereg()
1769 while (si_corereg(sih, idx, pmustatus_offset, 0, 0) & PST_SLOW_WR_PENDING) in si_pmu_corereg()
1773 return si_corereg(sih, idx, regoff, mask, val); in si_pmu_corereg()
1786 si_corereg_addr(si_t *sih, uint coreidx, uint regoff) in si_corereg_addr() argument
1788 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_corereg_addr()
1789 return sb_corereg_addr(sih, coreidx, regoff); in si_corereg_addr()
1790 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_corereg_addr()
1791 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_corereg_addr()
1792 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_corereg_addr()
1793 return ai_corereg_addr(sih, coreidx, regoff); in si_corereg_addr()
1800 si_core_disable(si_t *sih, uint32 bits) in si_core_disable() argument
1802 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_core_disable()
1803 sb_core_disable(sih, bits); in si_core_disable()
1804 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_core_disable()
1805 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_core_disable()
1806 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_core_disable()
1807 ai_core_disable(sih, bits); in si_core_disable()
1808 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in si_core_disable()
1809 ub_core_disable(sih, bits); in si_core_disable()
1813 si_core_reset(si_t *sih, uint32 bits, uint32 resetbits) in si_core_reset() argument
1815 if (CHIPTYPE(sih->socitype) == SOCI_SB) in si_core_reset()
1816 sb_core_reset(sih, bits, resetbits); in si_core_reset()
1817 else if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_core_reset()
1818 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_core_reset()
1819 (CHIPTYPE(sih->socitype) == SOCI_NAI)) in si_core_reset()
1820 ai_core_reset(sih, bits, resetbits); in si_core_reset()
1821 else if (CHIPTYPE(sih->socitype) == SOCI_UBUS) in si_core_reset()
1822 ub_core_reset(sih, bits, resetbits); in si_core_reset()
1827 si_corebist(si_t *sih) in si_corebist() argument
1833 cflags = si_core_cflags(sih, 0, 0); in si_corebist()
1836 si_core_cflags(sih, ~0, (SICF_BIST_EN | SICF_FGC)); in si_corebist()
1839 SPINWAIT(((si_core_sflags(sih, 0, 0) & SISF_BIST_DONE) == 0), 100000); in si_corebist()
1841 if (si_core_sflags(sih, 0, 0) & SISF_BIST_ERROR) in si_corebist()
1845 si_core_cflags(sih, 0xffff, cflags); in si_corebist()
1851 si_num_slaveports(si_t *sih, uint coreid) in si_num_slaveports() argument
1853 uint idx = si_findcoreidx(sih, coreid, 0); in si_num_slaveports()
1857 if (CHIPTYPE(sih->socitype) == SOCI_AI) { in si_num_slaveports()
1858 num = ai_num_slaveports(sih, idx); in si_num_slaveports()
1865 si_get_slaveport_addr(si_t *sih, uint spidx, uint baidx, uint core_id, uint coreunit) in si_get_slaveport_addr() argument
1867 si_info_t *sii = SI_INFO(sih); in si_get_slaveport_addr()
1871 if (!((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_get_slaveport_addr()
1872 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_get_slaveport_addr()
1873 (CHIPTYPE(sih->socitype) == SOCI_NAI))) in si_get_slaveport_addr()
1876 si_setcore(sih, core_id, coreunit); in si_get_slaveport_addr()
1878 addr = ai_addrspace(sih, spidx, baidx); in si_get_slaveport_addr()
1880 si_setcoreidx(sih, origidx); in si_get_slaveport_addr()
1887 si_get_d11_slaveport_addr(si_t *sih, uint spidx, uint baidx, uint coreunit) in si_get_d11_slaveport_addr() argument
1889 si_info_t *sii = SI_INFO(sih); in si_get_d11_slaveport_addr()
1893 if (!((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_get_d11_slaveport_addr()
1894 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS) || in si_get_d11_slaveport_addr()
1895 (CHIPTYPE(sih->socitype) == SOCI_NAI))) in si_get_d11_slaveport_addr()
1898 si_setcore(sih, D11_CORE_ID, coreunit); in si_get_d11_slaveport_addr()
1900 addr = ai_addrspace(sih, spidx, baidx); in si_get_d11_slaveport_addr()
1902 si_setcoreidx(sih, origidx); in si_get_d11_slaveport_addr()
2021 si_chip_hostif(si_t *sih) in si_chip_hostif() argument
2025 switch (CHIPID(sih->chip)) { in si_chip_hostif()
2041 if ((sih->chippkg & 0x1) && (sih->chipst & CST4360_MODE_USB)) in si_chip_hostif()
2050 if (CST4335_CHIPMODE_USB20D(sih->chipst)) in si_chip_hostif()
2052 else if (CST4335_CHIPMODE_SDIOD(sih->chipst)) in si_chip_hostif()
2059 if (CST4345_CHIPMODE_USB20D(sih->chipst) || CST4345_CHIPMODE_HSIC(sih->chipst)) in si_chip_hostif()
2061 else if (CST4345_CHIPMODE_SDIOD(sih->chipst)) in si_chip_hostif()
2063 else if (CST4345_CHIPMODE_PCIE(sih->chipst)) in si_chip_hostif()
2069 if (CST4349_CHIPMODE_SDIOD(sih->chipst)) in si_chip_hostif()
2071 else if (CST4349_CHIPMODE_PCIE(sih->chipst)) in si_chip_hostif()
2075 if (CST4364_CHIPMODE_SDIOD(sih->chipst)) in si_chip_hostif()
2077 else if (CST4364_CHIPMODE_PCIE(sih->chipst)) in si_chip_hostif()
2081 if (CST4373_CHIPMODE_USB20D(sih->chipst)) in si_chip_hostif()
2083 else if (CST4373_CHIPMODE_SDIOD(sih->chipst)) in si_chip_hostif()
2085 else if (CST4373_CHIPMODE_PCIE(sih->chipst)) in si_chip_hostif()
2090 if (CST4347_CHIPMODE_SDIOD(sih->chipst)) in si_chip_hostif()
2092 else if (CST4347_CHIPMODE_PCIE(sih->chipst)) in si_chip_hostif()
2096 if (CST4369_CHIPMODE_SDIOD(sih->chipst)) in si_chip_hostif()
2098 else if (CST4369_CHIPMODE_PCIE(sih->chipst)) in si_chip_hostif()
2116 if (CST4350_CHIPMODE_USB20D(sih->chipst) || in si_chip_hostif()
2117 CST4350_CHIPMODE_HSIC20D(sih->chipst) || in si_chip_hostif()
2118 CST4350_CHIPMODE_USB30D(sih->chipst) || in si_chip_hostif()
2119 CST4350_CHIPMODE_USB30D_WL(sih->chipst) || in si_chip_hostif()
2120 CST4350_CHIPMODE_HSIC30D(sih->chipst)) in si_chip_hostif()
2122 else if (CST4350_CHIPMODE_SDIOD(sih->chipst)) in si_chip_hostif()
2124 else if (CST4350_CHIPMODE_PCIE(sih->chipst)) in si_chip_hostif()
2137 si_watchdog(si_t *sih, uint ticks) in si_watchdog() argument
2142 if (PMUCTL_ENAB(sih) && pmu_wdt) { in si_watchdog()
2143 nb = (CCREV(sih->ccrev) < 26) ? 16 : ((CCREV(sih->ccrev) >= 37) ? 32 : 24); in si_watchdog()
2156 if (CHIPID(sih->chip) == BCM43012_CHIP_ID) { in si_watchdog()
2157 PMU_REG_NEW(sih, min_res_mask, ~0, DEFAULT_43012_MIN_RES_MASK); in si_watchdog()
2158 PMU_REG_NEW(sih, watchdog_res_mask, ~0, DEFAULT_43012_MIN_RES_MASK); in si_watchdog()
2159 PMU_REG_NEW(sih, pmustatus, PST_WDRESET, PST_WDRESET); in si_watchdog()
2160 PMU_REG_NEW(sih, pmucontrol_ext, PCTL_EXT_FASTLPO_SWENAB, 0); in si_watchdog()
2161 SPINWAIT((PMU_REG(sih, pmustatus, 0, 0) & PST_ILPFASTLPO), in si_watchdog()
2164 if (sih->chip == CYW55500_CHIP_ID || in si_watchdog()
2165 sih->chip == CYW55560_CHIP_ID) { in si_watchdog()
2166 si_corereg(sih, si_findcoreidx(sih, PMU_CORE_ID, 0), in si_watchdog()
2169 pmu_corereg(sih, SI_CC_IDX, pmuwatchdog, ~0, ticks); in si_watchdog()
2176 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, watchdog), ~0, ticks); in si_watchdog()
2182 si_watchdog_ms(si_t *sih, uint32 ms) in si_watchdog_ms() argument
2184 si_watchdog(sih, wd_msticks * ms); in si_watchdog_ms()
2193 si_taclear(si_t *sih, bool details) in si_taclear() argument
2288 si_clkctl_init(si_t *sih) in si_clkctl_init() argument
2295 if (!CCCTL_ENAB(sih)) in si_clkctl_init()
2298 sii = SI_INFO(sih); in si_clkctl_init()
2302 if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) in si_clkctl_init()
2309 if (CCREV(sih->ccrev) >= 10) in si_clkctl_init()
2318 si_setcoreidx(sih, origidx); in si_clkctl_init()
2323 si_gpiosetcore(si_t *sih) in si_gpiosetcore() argument
2325 return (si_setcoreidx(sih, SI_CC_IDX)); in si_gpiosetcore()
2335 si_gpiocontrol(si_t *sih, uint32 mask, uint32 val, uint8 priority) in si_gpiocontrol() argument
2345 (BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) { in si_gpiocontrol()
2352 return (si_corereg(sih, SI_CC_IDX, regoff, mask, val)); in si_gpiocontrol()
2357 si_gpioouten(si_t *sih, uint32 mask, uint32 val, uint8 priority) in si_gpioouten() argument
2367 (BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) { in si_gpioouten()
2374 return (si_corereg(sih, SI_CC_IDX, regoff, mask, val)); in si_gpioouten()
2379 si_gpioout(si_t *sih, uint32 mask, uint32 val, uint8 priority) in si_gpioout() argument
2389 (BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) { in si_gpioout()
2396 return (si_corereg(sih, SI_CC_IDX, regoff, mask, val)); in si_gpioout()
2401 si_gpioreserve(si_t *sih, uint32 gpio_bitmask, uint8 priority) in si_gpioreserve() argument
2406 if ((BUSTYPE(sih->bustype) != SI_BUS) || (!priority)) { in si_gpioreserve()
2407 ASSERT((BUSTYPE(sih->bustype) == SI_BUS) && (priority)); in si_gpioreserve()
2432 si_gpiorelease(si_t *sih, uint32 gpio_bitmask, uint8 priority) in si_gpiorelease() argument
2437 if ((BUSTYPE(sih->bustype) != SI_BUS) || (!priority)) { in si_gpiorelease()
2438 ASSERT((BUSTYPE(sih->bustype) == SI_BUS) && (priority)); in si_gpiorelease()
2459 si_gpioin(si_t *sih) in si_gpioin() argument
2464 return (si_corereg(sih, SI_CC_IDX, regoff, 0, 0)); in si_gpioin()
2469 si_gpiointpolarity(si_t *sih, uint32 mask, uint32 val, uint8 priority) in si_gpiointpolarity() argument
2474 if ((BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) { in si_gpiointpolarity()
2481 return (si_corereg(sih, SI_CC_IDX, regoff, mask, val)); in si_gpiointpolarity()
2486 si_gpiointmask(si_t *sih, uint32 mask, uint32 val, uint8 priority) in si_gpiointmask() argument
2491 if ((BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) { in si_gpiointmask()
2498 return (si_corereg(sih, SI_CC_IDX, regoff, mask, val)); in si_gpiointmask()
2502 si_gpioeventintmask(si_t *sih, uint32 mask, uint32 val, uint8 priority) in si_gpioeventintmask() argument
2506 if ((BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) { in si_gpioeventintmask()
2512 return (si_corereg(sih, SI_CC_IDX, regoff, mask, val)); in si_gpioeventintmask()
2517 si_gpioled(si_t *sih, uint32 mask, uint32 val) in si_gpioled() argument
2519 if (CCREV(sih->ccrev) < 16) in si_gpioled()
2523 return (si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gpiotimeroutmask), mask, val)); in si_gpioled()
2528 si_gpiotimerval(si_t *sih, uint32 mask, uint32 gpiotimerval) in si_gpiotimerval() argument
2530 if (CCREV(sih->ccrev) < 16) in si_gpiotimerval()
2533 return (si_corereg(sih, SI_CC_IDX, in si_gpiotimerval()
2538 si_gpiopull(si_t *sih, bool updown, uint32 mask, uint32 val) in si_gpiopull() argument
2542 if (CCREV(sih->ccrev) < 20) in si_gpiopull()
2546 return (si_corereg(sih, SI_CC_IDX, offs, mask, val)); in si_gpiopull()
2550 si_gpioevent(si_t *sih, uint regtype, uint32 mask, uint32 val) in si_gpioevent() argument
2554 if (CCREV(sih->ccrev) < 11) in si_gpioevent()
2566 return (si_corereg(sih, SI_CC_IDX, offs, mask, val)); in si_gpioevent()
2570 si_gpio_int_enable(si_t *sih, bool enable) in si_gpio_int_enable() argument
2574 if (CCREV(sih->ccrev) < 11) in si_gpio_int_enable()
2578 return (si_corereg(sih, SI_CC_IDX, offs, CI_GPIO, (enable ? CI_GPIO : 0))); in si_gpio_int_enable()
2596 si_sysmem_size(si_t *sih) in si_sysmem_size() argument
2598 si_info_t *sii = SI_INFO(sih); in si_sysmem_size()
2611 origidx = si_coreidx(sih); in si_sysmem_size()
2614 if (!(regs = si_setcore(sih, SYSMEM_CORE_ID, 0))) in si_sysmem_size()
2618 if (!(wasup = si_iscoreup(sih))) in si_sysmem_size()
2619 si_core_reset(sih, 0, 0); in si_sysmem_size()
2629 si_setcoreidx(sih, origidx); in si_sysmem_size()
2652 void si_socram_set_bankpda(si_t *sih, uint32 bankidx, uint32 bankpda) in si_socram_set_bankpda() argument
2654 si_info_t *sii = SI_INFO(sih); in si_socram_set_bankpda()
2663 origidx = si_coreidx(sih); in si_socram_set_bankpda()
2666 if (!(regs = si_setcore(sih, SOCRAM_CORE_ID, 0))) in si_socram_set_bankpda()
2669 if (!(wasup = si_iscoreup(sih))) in si_socram_set_bankpda()
2670 si_core_reset(sih, 0, 0); in si_socram_set_bankpda()
2672 corerev = si_corerev(sih); in si_socram_set_bankpda()
2680 si_core_disable(sih, 0); in si_socram_set_bankpda()
2681 si_setcoreidx(sih, origidx); in si_socram_set_bankpda()
2688 si_socdevram(si_t *sih, bool set, uint8 *enable, uint8 *protect, uint8 *remap) in si_socdevram() argument
2690 si_info_t *sii = SI_INFO(sih); in si_socdevram()
2699 origidx = si_coreidx(sih); in si_socdevram()
2705 if (!(regs = si_setcore(sih, SOCRAM_CORE_ID, 0))) in si_socdevram()
2709 if (!(wasup = si_iscoreup(sih))) in si_socdevram()
2710 si_core_reset(sih, 0, 0); in si_socdevram()
2712 corerev = si_corerev(sih); in si_socdevram()
2752 si_core_disable(sih, 0); in si_socdevram()
2753 si_setcoreidx(sih, origidx); in si_socdevram()
2760 si_socdevram_remap_isenb(si_t *sih) in si_socdevram_remap_isenb() argument
2762 si_info_t *sii = SI_INFO(sih); in si_socdevram_remap_isenb()
2775 origidx = si_coreidx(sih); in si_socdevram_remap_isenb()
2778 if (!(regs = si_setcore(sih, SOCRAM_CORE_ID, 0))) in si_socdevram_remap_isenb()
2782 if (!(wasup = si_iscoreup(sih))) in si_socdevram_remap_isenb()
2783 si_core_reset(sih, 0, 0); in si_socdevram_remap_isenb()
2785 corerev = si_corerev(sih); in si_socdevram_remap_isenb()
2802 si_core_disable(sih, 0); in si_socdevram_remap_isenb()
2803 si_setcoreidx(sih, origidx); in si_socdevram_remap_isenb()
2811 si_socdevram_pkg(si_t *sih) in si_socdevram_pkg() argument
2813 if (si_socdevram_size(sih) > 0) in si_socdevram_pkg()
2820 si_socdevram_size(si_t *sih) in si_socdevram_size() argument
2822 si_info_t *sii = SI_INFO(sih); in si_socdevram_size()
2832 origidx = si_coreidx(sih); in si_socdevram_size()
2835 if (!(regs = si_setcore(sih, SOCRAM_CORE_ID, 0))) in si_socdevram_size()
2839 if (!(wasup = si_iscoreup(sih))) in si_socdevram_size()
2840 si_core_reset(sih, 0, 0); in si_socdevram_size()
2842 corerev = si_corerev(sih); in si_socdevram_size()
2856 si_core_disable(sih, 0); in si_socdevram_size()
2857 si_setcoreidx(sih, origidx); in si_socdevram_size()
2866 si_socdevram_remap_size(si_t *sih) in si_socdevram_remap_size() argument
2868 si_info_t *sii = SI_INFO(sih); in si_socdevram_remap_size()
2882 origidx = si_coreidx(sih); in si_socdevram_remap_size()
2885 if (!(regs = si_setcore(sih, SOCRAM_CORE_ID, 0))) in si_socdevram_remap_size()
2889 if (!(wasup = si_iscoreup(sih))) in si_socdevram_remap_size()
2890 si_core_reset(sih, 0, 0); in si_socdevram_remap_size()
2892 corerev = si_corerev(sih); in si_socdevram_remap_size()
2920 si_core_disable(sih, 0); in si_socdevram_remap_size()
2921 si_setcoreidx(sih, origidx); in si_socdevram_remap_size()
2931 si_socram_size(si_t *sih) in si_socram_size() argument
2933 si_info_t *sii = SI_INFO(sih); in si_socram_size()
2945 origidx = si_coreidx(sih); in si_socram_size()
2948 if (!(regs = si_setcore(sih, SOCRAM_CORE_ID, 0))) in si_socram_size()
2952 if (!(wasup = si_iscoreup(sih))) in si_socram_size()
2953 si_core_reset(sih, 0, 0); in si_socram_size()
2954 corerev = si_corerev(sih); in si_socram_size()
2987 si_core_disable(sih, 0); in si_socram_size()
2988 si_setcoreidx(sih, origidx); in si_socram_size()
2998 si_tcm_size(si_t *sih) in si_tcm_size() argument
3000 si_info_t *sii = SI_INFO(sih); in si_tcm_size()
3019 origidx = si_coreidx(sih); in si_tcm_size()
3022 if (!(regs = si_setcore(sih, ARMCR4_CORE_ID, 0))) in si_tcm_size()
3028 if (!sih->secureboot) { in si_tcm_size()
3029 if (!(wasup = si_iscoreup(sih))) in si_tcm_size()
3030 si_core_reset(sih, SICF_CPUHALT, SICF_CPUHALT); in si_tcm_size()
3055 if (!sih->secureboot) { in si_tcm_size()
3057 si_core_disable(sih, 0); in si_tcm_size()
3059 si_setcoreidx(sih, origidx); in si_tcm_size()
3068 si_has_flops(si_t *sih) in si_has_flops() argument
3073 origidx = si_coreidx(sih); in si_has_flops()
3074 if (si_setcore(sih, ARMCR4_CORE_ID, 0)) { in si_has_flops()
3075 cr4_rev = si_corerev(sih); in si_has_flops()
3076 si_setcoreidx(sih, origidx); in si_has_flops()
3085 si_socram_srmem_size(si_t *sih) in si_socram_srmem_size() argument
3087 si_info_t *sii = SI_INFO(sih); in si_socram_srmem_size()
3097 if (CHIPID(sih->chip) == BCM43430_CHIP_ID || in si_socram_srmem_size()
3098 CHIPID(sih->chip) == BCM43018_CHIP_ID) { in si_socram_srmem_size()
3104 origidx = si_coreidx(sih); in si_socram_srmem_size()
3107 if (!(regs = si_setcore(sih, SOCRAM_CORE_ID, 0))) in si_socram_srmem_size()
3111 if (!(wasup = si_iscoreup(sih))) in si_socram_srmem_size()
3112 si_core_reset(sih, 0, 0); in si_socram_srmem_size()
3113 corerev = si_corerev(sih); in si_socram_srmem_size()
3129 si_core_disable(sih, 0); in si_socram_srmem_size()
3130 si_setcoreidx(sih, origidx); in si_socram_srmem_size()
3140 si_btcgpiowar(si_t *sih) in si_btcgpiowar() argument
3142 si_info_t *sii = SI_INFO(sih); in si_btcgpiowar()
3150 if (!(sih->cccaps & CC_CAP_UARTGPIO)) in si_btcgpiowar()
3156 origidx = si_coreidx(sih); in si_btcgpiowar()
3158 cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0); in si_btcgpiowar()
3164 si_setcoreidx(sih, origidx); in si_btcgpiowar()
3170 si_chipcontrl_restore(si_t *sih, uint32 val) in si_chipcontrl_restore() argument
3172 si_info_t *sii = SI_INFO(sih); in si_chipcontrl_restore()
3174 uint origidx = si_coreidx(sih); in si_chipcontrl_restore()
3176 if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) { in si_chipcontrl_restore()
3181 si_setcoreidx(sih, origidx); in si_chipcontrl_restore()
3185 si_chipcontrl_read(si_t *sih) in si_chipcontrl_read() argument
3187 si_info_t *sii = SI_INFO(sih); in si_chipcontrl_read()
3189 uint origidx = si_coreidx(sih); in si_chipcontrl_read()
3192 if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) { in si_chipcontrl_read()
3197 si_setcoreidx(sih, origidx); in si_chipcontrl_read()
3203 si_chipcontrl_srom4360(si_t *sih, bool on) in si_chipcontrl_srom4360() argument
3205 si_info_t *sii = SI_INFO(sih); in si_chipcontrl_srom4360()
3207 uint origidx = si_coreidx(sih); in si_chipcontrl_srom4360()
3210 if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) { in si_chipcontrl_srom4360()
3227 si_setcoreidx(sih, origidx); in si_chipcontrl_srom4360()
3235 si_srom_clk_set(si_t *sih) in si_srom_clk_set() argument
3237 si_info_t *sii = SI_INFO(sih); in si_srom_clk_set()
3239 uint origidx = si_coreidx(sih); in si_srom_clk_set()
3243 if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) { in si_srom_clk_set()
3249 if (BCM4365_CHIP(sih->chip)) { in si_srom_clk_set()
3256 si_setcoreidx(sih, origidx); in si_srom_clk_set()
3261 si_pmu_avb_clk_set(si_t *sih, osl_t *osh, bool set_flag) in si_pmu_avb_clk_set() argument
3266 si_btc_enable_chipcontrol(si_t *sih) in si_btc_enable_chipcontrol() argument
3268 si_info_t *sii = SI_INFO(sih); in si_btc_enable_chipcontrol()
3270 uint origidx = si_coreidx(sih); in si_btc_enable_chipcontrol()
3272 if ((cc = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0)) == NULL) { in si_btc_enable_chipcontrol()
3281 si_setcoreidx(sih, origidx); in si_btc_enable_chipcontrol()
3285 void si_set_device_removed(si_t *sih, bool status) in si_set_device_removed() argument
3287 si_info_t *sii = SI_INFO(sih); in si_set_device_removed()
3294 si_deviceremoved(si_t *sih) in si_deviceremoved() argument
3297 si_info_t *sii = SI_INFO(sih); in si_deviceremoved()
3303 switch (BUSTYPE(sih->bustype)) { in si_deviceremoved()
3305 ASSERT(SI_INFO(sih)->osh != NULL); in si_deviceremoved()
3306 w = OSL_PCI_READ_CONFIG(SI_INFO(sih)->osh, PCI_CFG_VID, sizeof(uint32)); in si_deviceremoved()
3326 si_is_sprom_available(si_t *sih) in si_is_sprom_available() argument
3328 if (CCREV(sih->ccrev) >= 31) { in si_is_sprom_available()
3334 if ((sih->cccaps & CC_CAP_SROM) == 0) in si_is_sprom_available()
3337 sii = SI_INFO(sih); in si_is_sprom_available()
3339 cc = si_setcoreidx(sih, SI_CC_IDX); in si_is_sprom_available()
3342 si_setcoreidx(sih, origidx); in si_is_sprom_available()
3346 switch (CHIPID(sih->chip)) { in si_is_sprom_available()
3352 return ((sih->chipst & CST4335_SPROM_MASK) && in si_is_sprom_available()
3353 !(sih->chipst & CST4335_SFLASH_MASK)); in si_is_sprom_available()
3355 return (sih->chipst & CST4349_SPROM_PRESENT) != 0; in si_is_sprom_available()
3359 return (sih->chipst & CST4364_SPROM_PRESENT) != 0; in si_is_sprom_available()
3361 if (CHIPREV(sih->chiprev) == 0) { in si_is_sprom_available()
3365 return (sih->chipst & CST4369_SPROM_PRESENT) != 0; in si_is_sprom_available()
3372 return (sih->chipst & CST4347_SPROM_PRESENT) != 0; in si_is_sprom_available()
3383 return (sih->chipst & CST4350_SPROM_PRESENT) != 0; in si_is_sprom_available()
3385 return (sih->chipst & CST43602_SPROM_PRESENT) != 0; in si_is_sprom_available()
3389 return (sih->chipst & CST43228_OTP_PRESENT) != CST43228_OTP_PRESENT; in si_is_sprom_available()
3398 uint32 si_get_sromctl(si_t *sih) in si_get_sromctl() argument
3401 uint origidx = si_coreidx(sih); in si_get_sromctl()
3403 osl_t *osh = si_osh(sih); in si_get_sromctl()
3405 cc = si_setcoreidx(sih, SI_CC_IDX); in si_get_sromctl()
3411 si_setcoreidx(sih, origidx); in si_get_sromctl()
3415 int si_set_sromctl(si_t *sih, uint32 value) in si_set_sromctl() argument
3418 uint origidx = si_coreidx(sih); in si_set_sromctl()
3419 osl_t *osh = si_osh(sih); in si_set_sromctl()
3422 cc = si_setcoreidx(sih, SI_CC_IDX); in si_set_sromctl()
3426 if (si_corerev(sih) >= 32) { in si_set_sromctl()
3441 si_setcoreidx(sih, origidx); in si_set_sromctl()
3447 si_core_wrapperreg(si_t *sih, uint32 coreidx, uint32 offset, uint32 mask, uint32 val) in si_core_wrapperreg() argument
3451 si_info_t *sii = SI_INFO(sih); in si_core_wrapperreg()
3453 origidx = si_coreidx(sih); in si_core_wrapperreg()
3456 si_setcoreidx(sih, coreidx); in si_core_wrapperreg()
3458 ret_val = si_wrapperreg(sih, offset, mask, val); in si_core_wrapperreg()
3461 si_setcoreidx(sih, origidx); in si_core_wrapperreg()
3472 si_pmu_res_req_timer_clr(si_t *sih) in si_pmu_res_req_timer_clr() argument
3479 pmu_corereg(sih, SI_CC_IDX, res_req_timer, mask, 0); in si_pmu_res_req_timer_clr()
3481 return pmu_corereg(sih, SI_CC_IDX, res_req_timer, 0, 0); in si_pmu_res_req_timer_clr()
3486 si_pmu_rfldo(si_t *sih, bool on) in si_pmu_rfldo() argument
3494 si_pcie_disable_oobselltr(si_t *sih) in si_pcie_disable_oobselltr() argument
3496 ASSERT(si_coreid(sih) == PCIE2_CORE_ID); in si_pcie_disable_oobselltr()
3497 if (PCIECOREREV(sih->buscorerev) >= 23) in si_pcie_disable_oobselltr()
3498 si_wrapperreg(sih, AI_OOBSELIND74, ~0, 0); in si_pcie_disable_oobselltr()
3500 si_wrapperreg(sih, AI_OOBSELIND30, ~0, 0); in si_pcie_disable_oobselltr()
3504 si_pcie_ltr_war(si_t *sih) in si_pcie_ltr_war() argument
3509 si_pcie_hw_LTR_war(si_t *sih) in si_pcie_hw_LTR_war() argument
3514 si_pciedev_reg_pm_clk_period(si_t *sih) in si_pciedev_reg_pm_clk_period() argument
3519 si_pciedev_crwlpciegen2(si_t *sih) in si_pciedev_crwlpciegen2() argument
3524 si_pcie_prep_D3(si_t *sih, bool enter_D3) in si_pcie_prep_D3() argument
3530 si_clear_backplane_to_per_core(si_t *sih, uint coreid, uint coreunit, void * wrap) in si_clear_backplane_to_per_core() argument
3532 if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_clear_backplane_to_per_core()
3533 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS)) { in si_clear_backplane_to_per_core()
3534 return ai_clear_backplane_to_per_core(sih, coreid, coreunit, wrap); in si_clear_backplane_to_per_core()
3542 si_clear_backplane_to(si_t *sih) in si_clear_backplane_to() argument
3544 if ((CHIPTYPE(sih->socitype) == SOCI_AI) || in si_clear_backplane_to()
3545 (CHIPTYPE(sih->socitype) == SOCI_DVTBUS)) { in si_clear_backplane_to()
3546 return ai_clear_backplane_to(sih); in si_clear_backplane_to()
3553 si_update_backplane_timeouts(si_t *sih, bool enable, uint32 timeout_exp, uint32 cid) in si_update_backplane_timeouts() argument
3557 if (CHIPTYPE(sih->socitype) != SOCI_AI) { in si_update_backplane_timeouts()
3561 ai_update_backplane_timeouts(sih, enable, timeout_exp, cid); in si_update_backplane_timeouts()
3570 si_slave_wrapper_add(si_t *sih) in si_slave_wrapper_add() argument
3576 if ((CHIPTYPE(sih->socitype) != SOCI_AI) && in si_slave_wrapper_add()
3577 (CHIPTYPE(sih->socitype) != SOCI_DVTBUS)) { in si_slave_wrapper_add()
3581 if (CHIPID(sih->chip) == BCM4345_CHIP_ID && CHIPREV(sih->chiprev) >= 6) { in si_slave_wrapper_add()
3582 si_info_t *sii = SI_INFO(sih); in si_slave_wrapper_add()
3597 if (BCM4347_CHIP(sih->chip)) { in si_slave_wrapper_add()
3605 ai_update_backplane_timeouts(sih, TRUE, axi_to, 0); in si_slave_wrapper_add()
3608 ai_update_backplane_timeouts(sih, FALSE, 0, PCIE_CORE_ID); in si_slave_wrapper_add()
3609 ai_update_backplane_timeouts(sih, FALSE, 0, PCIE2_CORE_ID); in si_slave_wrapper_add()
3617 si_pll_sr_reinit(si_t *sih) in si_pll_sr_reinit() argument
3625 si_config_4364_d11_oob(si_t *sih, uint coreid) in si_config_4364_d11_oob() argument
3629 save_idx = si_coreidx(sih); in si_config_4364_d11_oob()
3630 si_setcore(sih, coreid, 0); in si_config_4364_d11_oob()
3631 si_wrapperreg(sih, AI_OOBSELINC30, ~0, 0x81828180); in si_config_4364_d11_oob()
3632 si_wrapperreg(sih, AI_OOBSELINC74, ~0, 0x87868183); in si_config_4364_d11_oob()
3633 si_wrapperreg(sih, AI_OOBSELOUTB74, ~0, 0x84858484); in si_config_4364_d11_oob()
3634 si_setcore(sih, coreid, 1); in si_config_4364_d11_oob()
3635 si_wrapperreg(sih, AI_OOBSELINC30, ~0, 0x81828180); in si_config_4364_d11_oob()
3636 si_wrapperreg(sih, AI_OOBSELINC74, ~0, 0x87868184); in si_config_4364_d11_oob()
3637 si_wrapperreg(sih, AI_OOBSELOUTB74, ~0, 0x84868484); in si_config_4364_d11_oob()
3638 si_setcoreidx(sih, save_idx); in si_config_4364_d11_oob()
3642 si_pll_closeloop(si_t *sih) in si_pll_closeloop() argument
3648 switch (CHIPID(sih->chip)) { in si_pll_closeloop()
3652 if (SR_ENAB() && sr_isenab(sih)) { in si_pll_closeloop()
3654 data = si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL8, 0, 0); in si_pll_closeloop()
3657 si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL8, in si_pll_closeloop()
3659 si_pmu_pllupd(sih); in si_pll_closeloop()
3666 si_pmu_chipcontrol(sih, PMU_CHIPCTL1, in si_pll_closeloop()
3682 #define PWRREQ_OFFSET(sih) OFFSETOF(chipcregs_t, powerctl) argument
3685 si_corereg_pciefast_write(si_t *sih, uint regoff, uint val) in si_corereg_pciefast_write() argument
3688 si_info_t *sii = SI_INFO(sih); in si_corereg_pciefast_write()
3690 ASSERT((BUSTYPE(sih->bustype) == PCI_BUS)); in si_corereg_pciefast_write()
3699 si_corereg_pciefast_read(si_t *sih, uint regoff) in si_corereg_pciefast_read() argument
3702 si_info_t *sii = SI_INFO(sih); in si_corereg_pciefast_read()
3704 ASSERT((BUSTYPE(sih->bustype) == PCI_BUS)); in si_corereg_pciefast_read()
3713 si_srpwr_request(si_t *sih, uint32 mask, uint32 val) in si_srpwr_request() argument
3715 uint32 r, offset = (BUSTYPE(sih->bustype) == SI_BUS) ? in si_srpwr_request()
3716 OFFSETOF(chipcregs_t, powerctl) : PWRREQ_OFFSET(sih); in si_srpwr_request()
3719 volatile uint32 *fast_srpwr_addr = (volatile uint32 *)((uintptr)SI_ENUM_BASE(sih) in si_srpwr_request()
3727 if (BUSTYPE(sih->bustype) == SI_BUS) { in si_srpwr_request()
3730 r = si_corereg_pciefast_read(sih, offset); in si_srpwr_request()
3739 if (BUSTYPE(sih->bustype) == SI_BUS) { in si_srpwr_request()
3743 si_corereg_pciefast_write(sih, offset, r); in si_srpwr_request()
3744 r = si_corereg_pciefast_read(sih, offset); in si_srpwr_request()
3752 si_srpwr_stat_spinwait(sih, mask2, val2); in si_srpwr_request()
3755 if (BUSTYPE(sih->bustype) == SI_BUS) { in si_srpwr_request()
3758 r = si_corereg_pciefast_read(sih, offset); in si_srpwr_request()
3766 si_srpwr_stat_spinwait(si_t *sih, uint32 mask, uint32 val) in si_srpwr_stat_spinwait() argument
3768 uint32 r, offset = (BUSTYPE(sih->bustype) == SI_BUS) ? in si_srpwr_stat_spinwait()
3769 OFFSETOF(chipcregs_t, powerctl) : PWRREQ_OFFSET(sih); in si_srpwr_stat_spinwait()
3770 volatile uint32 *fast_srpwr_addr = (volatile uint32 *)((uintptr)SI_ENUM_BASE(sih) in si_srpwr_stat_spinwait()
3780 if (BUSTYPE(sih->bustype) == SI_BUS) { in si_srpwr_stat_spinwait()
3786 SPINWAIT(((si_corereg_pciefast_read(sih, offset) & mask) != val), in si_srpwr_stat_spinwait()
3788 r = si_corereg_pciefast_read(sih, offset) & mask; in si_srpwr_stat_spinwait()
3792 r = (r >> SRPWR_STATUS_SHIFT) & SRPWR_DMN_ALL_MASK(sih); in si_srpwr_stat_spinwait()
3798 si_srpwr_stat(si_t *sih) in si_srpwr_stat() argument
3800 uint32 r, offset = (BUSTYPE(sih->bustype) == SI_BUS) ? in si_srpwr_stat()
3801 OFFSETOF(chipcregs_t, powerctl) : PWRREQ_OFFSET(sih); in si_srpwr_stat()
3802 uint cidx = (BUSTYPE(sih->bustype) == SI_BUS) ? SI_CC_IDX : sih->buscoreidx; in si_srpwr_stat()
3804 if (BUSTYPE(sih->bustype) == SI_BUS) { in si_srpwr_stat()
3805 r = si_corereg(sih, cidx, offset, 0, 0); in si_srpwr_stat()
3807 r = si_corereg_pciefast_read(sih, offset); in si_srpwr_stat()
3810 r = (r >> SRPWR_STATUS_SHIFT) & SRPWR_DMN_ALL_MASK(sih); in si_srpwr_stat()
3816 si_srpwr_domain(si_t *sih) in si_srpwr_domain() argument
3818 uint32 r, offset = (BUSTYPE(sih->bustype) == SI_BUS) ? in si_srpwr_domain()
3819 OFFSETOF(chipcregs_t, powerctl) : PWRREQ_OFFSET(sih); in si_srpwr_domain()
3820 uint cidx = (BUSTYPE(sih->bustype) == SI_BUS) ? SI_CC_IDX : sih->buscoreidx; in si_srpwr_domain()
3822 if (BUSTYPE(sih->bustype) == SI_BUS) { in si_srpwr_domain()
3823 r = si_corereg(sih, cidx, offset, 0, 0); in si_srpwr_domain()
3825 r = si_corereg_pciefast_read(sih, offset); in si_srpwr_domain()
3834 si_srpwr_domain_all_mask(si_t *sih) in si_srpwr_domain_all_mask() argument
3841 if (si_scan_core_present(sih)) { in si_srpwr_domain_all_mask()
3852 si_raw_reg(si_t *sih, uint32 reg, uint32 val, uint32 wrire_req) in si_raw_reg() argument
3854 si_info_t *sii = SI_INFO(sih); in si_raw_reg()
3865 if (BUSTYPE(sih->bustype) == SI_BUS) { in si_raw_reg()
3870 if (BUSTYPE(sih->bustype) != PCI_BUS) { in si_raw_reg()
3917 si_lhl_ps_mode(si_t *sih) in si_lhl_ps_mode() argument
3919 si_info_t *sii = SI_INFO(sih); in si_lhl_ps_mode()
3924 BCMRAMFN(si_scan_core_present)(si_t *sih) in BCMRAMFN()
3926 return ((si_numcoreunits(sih, D11_CORE_ID) >= 2) && in BCMRAMFN()
3927 (si_numcoreunits(sih, SR_CORE_ID) > 4)); in BCMRAMFN()