100 #define PMUREGS_ILP_SENSITIVE(regoff) \  argument
101 	((regoff) == OFFSETOF(pmuregs_t, pmutimer) || \
102 	 (regoff) == OFFSETOF(pmuregs_t, pmuwatchdog) || \
103 	 (regoff) == OFFSETOF(pmuregs_t, res_req_timer))
105 #define CHIPCREGS_ILP_SENSITIVE(regoff) \  argument
106 	((regoff) == OFFSETOF(chipcregs_t, pmutimer) || \
107 	 (regoff) == OFFSETOF(chipcregs_t, pmuwatchdog) || \
108 	 (regoff) == OFFSETOF(chipcregs_t, res_req_timer))
131 static bool si_pmu_is_ilp_sensitive(uint32 idx, uint regoff);
1722 si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)  in si_corereg()  argument
1725 		return sb_corereg(sih, coreidx, regoff, mask, val);  in si_corereg()
1729 		return ai_corereg(sih, coreidx, regoff, mask, val);  in si_corereg()
1731 		return ub_corereg(sih, coreidx, regoff, mask, val);  in si_corereg()
1739 si_corereg_writeonly(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)  in si_corereg_writeonly()  argument
1741 	return ai_corereg_writeonly(sih, coreidx, regoff, mask, val);  in si_corereg_writeonly()
1745 bool si_pmu_is_ilp_sensitive(uint32 idx, uint regoff)  in si_pmu_is_ilp_sensitive()  argument
1748 		if (CHIPCREGS_ILP_SENSITIVE(regoff))  in si_pmu_is_ilp_sensitive()
1750 	} else if (PMUREGS_ILP_SENSITIVE(regoff)) {  in si_pmu_is_ilp_sensitive()
1759 si_pmu_corereg(si_t *sih, uint32 idx, uint regoff, uint mask, uint val)  in si_pmu_corereg()  argument
1765 	    si_pmu_is_ilp_sensitive(idx, regoff)) {  in si_pmu_corereg()
1773 	return si_corereg(sih, idx, regoff, mask, val);  in si_pmu_corereg()
1786 si_corereg_addr(si_t *sih, uint coreidx, uint regoff)  in si_corereg_addr()  argument
1789 		return sb_corereg_addr(sih, coreidx, regoff);  in si_corereg_addr()
1793 		return ai_corereg_addr(sih, coreidx, regoff);  in si_corereg_addr()
2337 	uint regoff;  in si_gpiocontrol()  local
2339 	regoff = 0;  in si_gpiocontrol()
2351 	regoff = OFFSETOF(chipcregs_t, gpiocontrol);  in si_gpiocontrol()
2352 	return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));  in si_gpiocontrol()
2359 	uint regoff;  in si_gpioouten()  local
2361 	regoff = 0;  in si_gpioouten()
2373 	regoff = OFFSETOF(chipcregs_t, gpioouten);  in si_gpioouten()
2374 	return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));  in si_gpioouten()
2381 	uint regoff;  in si_gpioout()  local
2383 	regoff = 0;  in si_gpioout()
2395 	regoff = OFFSETOF(chipcregs_t, gpioout);  in si_gpioout()
2396 	return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));  in si_gpioout()
2461 	uint regoff;  in si_gpioin()  local
2463 	regoff = OFFSETOF(chipcregs_t, gpioin);  in si_gpioin()
2464 	return (si_corereg(sih, SI_CC_IDX, regoff, 0, 0));  in si_gpioin()
2471 	uint regoff;  in si_gpiointpolarity()  local
2480 	regoff = OFFSETOF(chipcregs_t, gpiointpolarity);  in si_gpiointpolarity()
2481 	return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));  in si_gpiointpolarity()
2488 	uint regoff;  in si_gpiointmask()  local
2497 	regoff = OFFSETOF(chipcregs_t, gpiointmask);  in si_gpiointmask()
2498 	return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));  in si_gpiointmask()
2504 	uint regoff;  in si_gpioeventintmask()  local
2511 	regoff = OFFSETOF(chipcregs_t, gpioeventintmask);  in si_gpioeventintmask()
2512 	return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));  in si_gpioeventintmask()
3685 si_corereg_pciefast_write(si_t *sih, uint regoff, uint val)  in si_corereg_pciefast_write()  argument
3693 		PCI_16KB0_PCIREGS_OFFSET + regoff);  in si_corereg_pciefast_write()
3699 si_corereg_pciefast_read(si_t *sih, uint regoff)  in si_corereg_pciefast_read()  argument
3707 		PCI_16KB0_PCIREGS_OFFSET + regoff);  in si_corereg_pciefast_read()