Lines Matching refs:R_REG

396 			sii->pub.chipst = R_REG(sii->osh, &cc->chipstatus);  in si_buscore_setup()
402 sii->pub.cccaps = R_REG(sii->osh, &cc->capabilities); in si_buscore_setup()
405 sii->pub.cccaps_ext = R_REG(sii->osh, &cc->capabilities_ext); in si_buscore_setup()
421 sii->pub.pmucaps = R_REG(sii->osh, &pmu->pmucapabilities); in si_buscore_setup()
428 sii->pub.pmucaps = R_REG(sii->osh, &cc->pmucapabilities); in si_buscore_setup()
747 erombase = R_REG(osh, &cc->eromptr); in si_doattach()
755 w = R_REG(osh, &sdioc->chipid); in si_doattach()
756 erombase = R_REG(osh, &sdioc->eromptr); in si_doattach()
758 erombase = R_REG(osh, &cc->eromptr); in si_doattach()
766 erombase = R_REG(osh, &cc->eromptr); in si_doattach()
794 w = R_REG(osh, &cc->chipid); in si_doattach()
887 clkdiv = R_REG(osh, &cc->clkdiv); in si_doattach()
899 capabilities = R_REG(osh, &cc->capabilities); in si_doattach()
903 sromprsnt = R_REG(osh, &cc->sromcontrol); in si_doattach()
907 clkdiv2 = (R_REG(osh, &cc->clkdiv2) & ~CLKD2_SROM); in si_doattach()
933 clkdiv = R_REG(osh, &cc->clkdiv); in si_doattach()
1103 return R_REG(sii->osh, ((uint32 *)(uintptr) in si_intflag()
1697 *val = R_REG(sii->osh, (volatile uint8*)r); in si_backplane_access()
1703 *val = R_REG(sii->osh, (volatile uint16*)r); in si_backplane_access()
1709 *val = R_REG(sii->osh, (volatile uint32*)r); in si_backplane_access()
2216 return (R_REG(sii->osh, &cc->slow_clk_ctl) & SCC_SS_MASK); in si_slowclk_src()
2231 ASSERT(R_REG(sii->osh, &cc->capabilities) & CC_CAP_PWR_CTL); in si_slowclk_freq()
2241 (((R_REG(sii->osh, &cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1); in si_slowclk_freq()
2252 div = R_REG(sii->osh, &cc->system_clk_ctl) >> SYCC_CD_SHIFT; in si_slowclk_freq()
2589 bankinfo = R_REG(sii->osh, &regs->bankinfo); in sysmem_banksize()
2620 coreinfo = R_REG(sii->osh, &regs->coreinfo); in si_sysmem_size()
2647 bankinfo = R_REG(sii->osh, &regs->bankinfo); in socram_banksize()
2719 extcinfo = R_REG(sii->osh, &regs->extracoreinfo); in si_socdevram()
2724 bankinfo = R_REG(sii->osh, &regs->bankinfo); in si_socdevram()
2787 extcinfo = R_REG(sii->osh, &regs->extracoreinfo); in si_socdevram_remap_isenb()
2792 bankinfo = R_REG(sii->osh, &regs->bankinfo); in si_socdevram_remap_isenb()
2848 extcinfo = R_REG(sii->osh, &regs->extracoreinfo); in si_socdevram_size()
2894 extcinfo = R_REG(sii->osh, &regs->extracoreinfo); in si_socdevram_remap_size()
2907 bankinfo = R_REG(sii->osh, &regs->bankinfo); in si_socdevram_remap_size()
2955 coreinfo = R_REG(sii->osh, &regs->coreinfo); in si_socram_size()
3034 corecap = R_REG(sii->osh, arm_cap_reg); in si_tcm_size()
3045 bxinfo = R_REG(sii->osh, arm_binfo); in si_tcm_size()
3114 coreinfo = R_REG(sii->osh, &regs->coreinfo); in si_socram_srmem_size()
3122 if (R_REG(sii->osh, &regs->bankinfo) & SOCRAM_BANKINFO_RETNTRAM_MASK) in si_socram_srmem_size()
3161 W_REG(sii->osh, &cc->uart0mcr, R_REG(sii->osh, &cc->uart0mcr) | 0x04); in si_btcgpiowar()
3196 val = R_REG(sii->osh, &cc->chipcontrol); in si_chipcontrl_read()
3214 val = R_REG(sii->osh, &cc->chipcontrol); in si_chipcontrl_srom4360()
3248 val = R_REG(sii->osh, &cc->clkdiv2); in si_srom_clk_set()
3279 R_REG(sii->osh, &cc->chipcontrol) | CC_BTCOEX_EN_MASK); in si_btc_enable_chipcontrol()
3341 sromctrl = R_REG(sii->osh, &cc->sromcontrol); in si_is_sprom_available()
3408 sromctl = R_REG(osh, &cc->sromcontrol); in si_get_sromctl()
3430 if ((R_REG(osh, &cc->capabilities) & CC_CAP_SROM) != 0 && in si_set_sromctl()
3431 (R_REG(osh, &cc->sromcontrol) & SRC_PRESENT)) { in si_set_sromctl()
3709 return R_REG(sii->osh, r); in si_corereg_pciefast_read()
3728 r = R_REG(OSH_NULL, fast_srpwr_addr); in si_srpwr_request()
3741 r = R_REG(OSH_NULL, fast_srpwr_addr); in si_srpwr_request()
3756 r = R_REG(OSH_NULL, fast_srpwr_addr); in si_srpwr_request()
3781 SPINWAIT(((R_REG(OSH_NULL, fast_srpwr_addr) & mask) != val), in si_srpwr_stat_spinwait()
3783 r = R_REG(OSH_NULL, fast_srpwr_addr) & mask; in si_srpwr_stat_spinwait()
3904 val = R_REG(sii->osh, addr); in si_raw_reg()