48 static uint _sb_coreidx(si_info_t *sii, uint32 sba);
49 static uint _sb_scan(si_info_t *sii, uint32 sba, volatile void *regs, uint bus, uint32 sbba,
51 static uint32 _sb_coresba(si_info_t *sii);
52 static volatile void *_sb_setcoreidx(si_info_t *sii, uint coreidx);
53 #define	SET_SBREG(sii, r, mask, val)	\  argument
54 		W_SBREG((sii), (r), ((R_SBREG((sii), (r)) & ~(mask)) | (val)))
61 #define	R_SBREG(sii, sbr)	sb_read_sbreg((sii), (sbr))  argument
62 #define	W_SBREG(sii, sbr, v)	sb_write_sbreg((sii), (sbr), (v))  argument
63 #define	AND_SBREG(sii, sbr, v)	W_SBREG((sii), (sbr), (R_SBREG((sii), (sbr)) & (v)))  argument
64 #define	OR_SBREG(sii, sbr, v)	W_SBREG((sii), (sbr), (R_SBREG((sii), (sbr)) | (v)))  argument
67 sb_read_sbreg(si_info_t *sii, volatile uint32 *sbr)  in sb_read_sbreg()  argument
78 	if (PCMCIA(sii)) {  in sb_read_sbreg()
79 		INTR_OFF(sii, intr_val);  in sb_read_sbreg()
81 		OSL_PCMCIA_WRITE_ATTR(sii->osh, MEM_SEG, &tmp, 1);  in sb_read_sbreg()
85 	val = R_REG(sii->osh, sbr);  in sb_read_sbreg()
87 	if (PCMCIA(sii)) {  in sb_read_sbreg()
89 		OSL_PCMCIA_WRITE_ATTR(sii->osh, MEM_SEG, &tmp, 1);  in sb_read_sbreg()
90 		INTR_RESTORE(sii, intr_val);  in sb_read_sbreg()
97 sb_write_sbreg(si_info_t *sii, volatile uint32 *sbr, uint32 v)  in sb_write_sbreg()  argument
109 	if (PCMCIA(sii)) {  in sb_write_sbreg()
110 		INTR_OFF(sii, intr_val);  in sb_write_sbreg()
112 		OSL_PCMCIA_WRITE_ATTR(sii->osh, MEM_SEG, &tmp, 1);  in sb_write_sbreg()
116 	if (BUSTYPE(sii->pub.bustype) == PCMCIA_BUS) {  in sb_write_sbreg()
117 		dummy = R_REG(sii->osh, sbr);  in sb_write_sbreg()
119 		W_REG(sii->osh, (volatile uint16 *)sbr, (uint16)(v & 0xffff));  in sb_write_sbreg()
120 		dummy = R_REG(sii->osh, sbr);  in sb_write_sbreg()
122 		W_REG(sii->osh, ((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));  in sb_write_sbreg()
124 		W_REG(sii->osh, sbr, v);  in sb_write_sbreg()
126 	if (PCMCIA(sii)) {  in sb_write_sbreg()
128 		OSL_PCMCIA_WRITE_ATTR(sii->osh, MEM_SEG, &tmp, 1);  in sb_write_sbreg()
129 		INTR_RESTORE(sii, intr_val);  in sb_write_sbreg()
136 	si_info_t *sii;  in sb_coreid()  local
139 	sii = SI_INFO(sih);  in sb_coreid()
140 	sb = REGS2SB(sii->curmap);  in sb_coreid()
142 	return ((R_SBREG(sii, &sb->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT);  in sb_coreid()
148 	si_info_t *sii = SI_INFO(sih);  in sb_intflag()  local
153 	INTR_OFF(sii, intr_val);  in sb_intflag()
158 	intflag = R_SBREG(sii, &sb->sbflagst);  in sb_intflag()
160 	INTR_RESTORE(sii, intr_val);  in sb_intflag()
168 	si_info_t *sii;  in sb_flag()  local
171 	sii = SI_INFO(sih);  in sb_flag()
172 	sb = REGS2SB(sii->curmap);  in sb_flag()
174 	return R_SBREG(sii, &sb->sbtpsflag) & SBTPS_NUM0_MASK;  in sb_flag()
180 	si_info_t *sii;  in sb_setint()  local
184 	sii = SI_INFO(sih);  in sb_setint()
185 	sb = REGS2SB(sii->curmap);  in sb_setint()
191 	W_SBREG(sii, &sb->sbintvec, vec);  in sb_setint()
196 _sb_coreidx(si_info_t *sii, uint32 sba)  in _sb_coreidx()  argument
199 	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;  in _sb_coreidx()
201 	for (i = 0; i < sii->numcores; i ++)  in _sb_coreidx()
209 _sb_coresba(si_info_t *sii)  in _sb_coresba()  argument
213 	switch (BUSTYPE(sii->pub.bustype)) {  in _sb_coresba()
215 		sbconfig_t *sb = REGS2SB(sii->curmap);  in _sb_coresba()
216 		sbaddr = sb_base(R_SBREG(sii, &sb->sbadmatch0));  in _sb_coresba()
221 		sbaddr = OSL_PCI_READ_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32));  in _sb_coresba()
226 		OSL_PCMCIA_READ_ATTR(sii->osh, PCMCIA_ADDR0, &tmp, 1);  in _sb_coresba()
228 		OSL_PCMCIA_READ_ATTR(sii->osh, PCMCIA_ADDR1, &tmp, 1);  in _sb_coresba()
230 		OSL_PCMCIA_READ_ATTR(sii->osh, PCMCIA_ADDR2, &tmp, 1);  in _sb_coresba()
238 		sbaddr = (uint32)(uintptr)sii->curmap;  in _sb_coresba()
253 	si_info_t *sii;  in sb_corevendor()  local
256 	sii = SI_INFO(sih);  in sb_corevendor()
257 	sb = REGS2SB(sii->curmap);  in sb_corevendor()
259 	return ((R_SBREG(sii, &sb->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT);  in sb_corevendor()
265 	si_info_t *sii;  in sb_corerev()  local
269 	sii = SI_INFO(sih);  in sb_corerev()
270 	sb = REGS2SB(sii->curmap);  in sb_corerev()
271 	sbidh = R_SBREG(sii, &sb->sbidhigh);  in sb_corerev()
280 	si_info_t *sii;  in sb_core_cflags_wo()  local
284 	sii = SI_INFO(sih);  in sb_core_cflags_wo()
285 	sb = REGS2SB(sii->curmap);  in sb_core_cflags_wo()
290 	w = (R_SBREG(sii, &sb->sbtmstatelow) & ~(mask << SBTML_SICF_SHIFT)) |  in sb_core_cflags_wo()
292 	W_SBREG(sii, &sb->sbtmstatelow, w);  in sb_core_cflags_wo()
299 	si_info_t *sii;  in sb_core_cflags()  local
303 	sii = SI_INFO(sih);  in sb_core_cflags()
304 	sb = REGS2SB(sii->curmap);  in sb_core_cflags()
310 		w = (R_SBREG(sii, &sb->sbtmstatelow) & ~(mask << SBTML_SICF_SHIFT)) |  in sb_core_cflags()
312 		W_SBREG(sii, &sb->sbtmstatelow, w);  in sb_core_cflags()
318 	return (R_SBREG(sii, &sb->sbtmstatelow) >> SBTML_SICF_SHIFT);  in sb_core_cflags()
325 	si_info_t *sii;  in sb_core_sflags()  local
329 	sii = SI_INFO(sih);  in sb_core_sflags()
330 	sb = REGS2SB(sii->curmap);  in sb_core_sflags()
337 		w = (R_SBREG(sii, &sb->sbtmstatehigh) & ~(mask << SBTMH_SISF_SHIFT)) |  in sb_core_sflags()
339 		W_SBREG(sii, &sb->sbtmstatehigh, w);  in sb_core_sflags()
343 	return (R_SBREG(sii, &sb->sbtmstatehigh) >> SBTMH_SISF_SHIFT);  in sb_core_sflags()
349 	si_info_t *sii;  in sb_iscoreup()  local
352 	sii = SI_INFO(sih);  in sb_iscoreup()
353 	sb = REGS2SB(sii->curmap);  in sb_iscoreup()
355 	return ((R_SBREG(sii, &sb->sbtmstatelow) &  in sb_iscoreup()
377 	si_info_t *sii = SI_INFO(sih);  in sb_corereg()  local
378 	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;  in sb_corereg()
387 	if (BUSTYPE(sii->pub.bustype) == SI_BUS) {  in sb_corereg()
397 	} else if (BUSTYPE(sii->pub.bustype) == PCI_BUS) {  in sb_corereg()
400 		if ((cores_info->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {  in sb_corereg()
404 			r = (volatile uint32 *)((volatile char *)sii->curmap +  in sb_corereg()
406 		} else if (sii->pub.buscoreidx == coreidx) {  in sb_corereg()
411 			if (SI_FAST(sii))  in sb_corereg()
412 				r = (volatile uint32 *)((volatile char *)sii->curmap +  in sb_corereg()
415 				r = (volatile uint32 *)((volatile char *)sii->curmap +  in sb_corereg()
423 		INTR_OFF(sii, intr_val);  in sb_corereg()
426 		origidx = si_coreidx(&sii->pub);  in sb_corereg()
429 		r = (volatile uint32*) ((volatile uchar*)sb_setcoreidx(&sii->pub, coreidx) +  in sb_corereg()
437 			w = (R_SBREG(sii, r) & ~mask) | val;  in sb_corereg()
438 			W_SBREG(sii, r, w);  in sb_corereg()
440 			w = (R_REG(sii->osh, r) & ~mask) | val;  in sb_corereg()
441 			W_REG(sii->osh, r, w);  in sb_corereg()
447 		w = R_SBREG(sii, r);  in sb_corereg()
449 		w = R_REG(sii->osh, r);  in sb_corereg()
455 			sb_setcoreidx(&sii->pub, origidx);  in sb_corereg()
457 		INTR_RESTORE(sii, intr_val);  in sb_corereg()
477 	si_info_t *sii = SI_INFO(sih);  in sb_corereg_addr()  local
478 	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;  in sb_corereg_addr()
486 	if (BUSTYPE(sii->pub.bustype) == SI_BUS) {  in sb_corereg_addr()
496 	} else if (BUSTYPE(sii->pub.bustype) == PCI_BUS) {  in sb_corereg_addr()
499 		if ((cores_info->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {  in sb_corereg_addr()
503 			r = (volatile uint32 *)((volatile char *)sii->curmap +  in sb_corereg_addr()
505 		} else if (sii->pub.buscoreidx == coreidx) {  in sb_corereg_addr()
510 			if (SI_FAST(sii))  in sb_corereg_addr()
511 				r = (volatile uint32 *)((volatile char *)sii->curmap +  in sb_corereg_addr()
514 				r = (volatile uint32 *)((volatile char *)sii->curmap +  in sb_corereg_addr()
536 _sb_scan(si_info_t *sii, uint32 sba, volatile void *regs, uint bus,  in _sb_scan()  argument
542 	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;  in _sb_scan()
553 	for (i = 0, next = sii->numcores; i < numcores && next < SB_BUS_MAXCORES; i++, next++) {  in _sb_scan()
557 		if ((BUSTYPE(sii->pub.bustype) == SI_BUS) && (cores_info->coresba[next] == sba)) {  in _sb_scan()
563 		sii->curmap = _sb_setcoreidx(sii, next);  in _sb_scan()
564 		sii->curidx = next;  in _sb_scan()
566 		cores_info->coreid[next] = sb_coreid(&sii->pub);  in _sb_scan()
571 			chipcregs_t *cc = (chipcregs_t *)sii->curmap;  in _sb_scan()
572 			uint32 ccrev = sb_corerev(&sii->pub);  in _sb_scan()
577 				numcores = (R_REG(sii->osh, &cc->chipid) & CID_CC_MASK) >>  in _sb_scan()
581 				uint chip = CHIPID(sii->pub.chip);  in _sb_scan()
595 				sii->pub.issim ? "QT" : ""));  in _sb_scan()
599 			sbconfig_t *sb = REGS2SB(sii->curmap);  in _sb_scan()
600 			uint32 nsbba = R_SBREG(sii, &sb->sbadmatch1);  in _sb_scan()
603 			sii->numcores = next + 1;  in _sb_scan()
608 			if (_sb_coreidx(sii, nsbba) != BADIDX)  in _sb_scan()
611 			nsbcc = (R_SBREG(sii, &sb->sbtmstatehigh) & 0x000f0000) >> 16;  in _sb_scan()
612 			nsbcc = _sb_scan(sii, sba, regs, bus + 1, nsbba, nsbcc, devid);  in _sb_scan()
621 	sii->numcores = i + ncc;  in _sb_scan()
622 	return sii->numcores;  in _sb_scan()
631 	si_info_t *sii = SI_INFO(sih);  in sb_scan()  local
634 	sb = REGS2SB(sii->curmap);  in sb_scan()
636 	sii->pub.socirev = (R_SBREG(sii, &sb->sbidlow) & SBIDL_RV_MASK) >> SBIDL_RV_SHIFT;  in sb_scan()
641 	origsba = _sb_coresba(sii);  in sb_scan()
644 	sii->numcores = _sb_scan(sii, origsba, regs, 0, si_enum_base(devid), 1, devid);  in sb_scan()
655 	si_info_t *sii = SI_INFO(sih);  in sb_setcoreidx()  local
657 	if (coreidx >= sii->numcores)  in sb_setcoreidx()
664 	ASSERT((sii->intrsenabled_fn == NULL) || !(*(sii)->intrsenabled_fn)((sii)->intr_arg));  in sb_setcoreidx()
666 	sii->curmap = _sb_setcoreidx(sii, coreidx);  in sb_setcoreidx()
667 	sii->curidx = coreidx;  in sb_setcoreidx()
669 	return (sii->curmap);  in sb_setcoreidx()
676 _sb_setcoreidx(si_info_t *sii, uint coreidx)  in _sb_setcoreidx()  argument
678 	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;  in _sb_setcoreidx()
682 	switch (BUSTYPE(sii->pub.bustype)) {  in _sb_setcoreidx()
694 		OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, sbaddr);  in _sb_setcoreidx()
695 		regs = sii->curmap;  in _sb_setcoreidx()
700 		OSL_PCMCIA_WRITE_ATTR(sii->osh, PCMCIA_ADDR0, &tmp, 1);  in _sb_setcoreidx()
702 		OSL_PCMCIA_WRITE_ATTR(sii->osh, PCMCIA_ADDR1, &tmp, 1);  in _sb_setcoreidx()
704 		OSL_PCMCIA_WRITE_ATTR(sii->osh, PCMCIA_ADDR2, &tmp, 1);  in _sb_setcoreidx()
705 		regs = sii->curmap;  in _sb_setcoreidx()
731 sb_admatch(si_info_t *sii, uint asidx)  in sb_admatch()  argument
736 	sb = REGS2SB(sii->curmap);  in sb_admatch()
767 	si_info_t *sii;  in sb_numaddrspaces()  local
770 	sii = SI_INFO(sih);  in sb_numaddrspaces()
771 	sb = REGS2SB(sii->curmap);  in sb_numaddrspaces()
774 	return ((R_SBREG(sii, &sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT) + 1;  in sb_numaddrspaces()
781 	si_info_t *sii;  in sb_addrspace()  local
783 	sii = SI_INFO(sih);  in sb_addrspace()
785 	return (sb_base(R_SBREG(sii, sb_admatch(sii, asidx))));  in sb_addrspace()
792 	si_info_t *sii;  in sb_addrspacesize()  local
794 	sii = SI_INFO(sih);  in sb_addrspacesize()
796 	return (sb_size(R_SBREG(sii, sb_admatch(sii, asidx))));  in sb_addrspacesize()
803 	si_info_t *sii = SI_INFO(sih);  in sb_commit()  local
807 	origidx = sii->curidx;  in sb_commit()
810 	INTR_OFF(sii, intr_val);  in sb_commit()
813 	if (sii->pub.ccrev != NOREV) {  in sb_commit()
818 		W_REG(sii->osh, &ccregs->broadcastaddress, SB_COMMIT);  in sb_commit()
819 		W_REG(sii->osh, &ccregs->broadcastdata, 0x0);  in sb_commit()
825 	INTR_RESTORE(sii, intr_val);  in sb_commit()
831 	si_info_t *sii;  in sb_core_disable()  local
835 	sii = SI_INFO(sih);  in sb_core_disable()
837 	ASSERT(GOODREGS(sii->curmap));  in sb_core_disable()
838 	sb = REGS2SB(sii->curmap);  in sb_core_disable()
841 	if (R_SBREG(sii, &sb->sbtmstatelow) & SBTML_RESET)  in sb_core_disable()
845 	if ((R_SBREG(sii, &sb->sbtmstatelow) & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) == 0)  in sb_core_disable()
849 	OR_SBREG(sii, &sb->sbtmstatelow, SBTML_REJ);  in sb_core_disable()
850 	dummy = R_SBREG(sii, &sb->sbtmstatelow);  in sb_core_disable()
853 	SPINWAIT((R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000);  in sb_core_disable()
854 	if (R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_BUSY)  in sb_core_disable()
857 	if (R_SBREG(sii, &sb->sbidlow) & SBIDL_INIT) {  in sb_core_disable()
858 		OR_SBREG(sii, &sb->sbimstate, SBIM_RJ);  in sb_core_disable()
859 		dummy = R_SBREG(sii, &sb->sbimstate);  in sb_core_disable()
862 		SPINWAIT((R_SBREG(sii, &sb->sbimstate) & SBIM_BY), 100000);  in sb_core_disable()
866 	W_SBREG(sii, &sb->sbtmstatelow,  in sb_core_disable()
869 	dummy = R_SBREG(sii, &sb->sbtmstatelow);  in sb_core_disable()
874 	if (R_SBREG(sii, &sb->sbidlow) & SBIDL_INIT)  in sb_core_disable()
875 		AND_SBREG(sii, &sb->sbimstate, ~SBIM_RJ);  in sb_core_disable()
879 	W_SBREG(sii, &sb->sbtmstatelow, ((bits << SBTML_SICF_SHIFT) | SBTML_REJ | SBTML_RESET));  in sb_core_disable()
891 	si_info_t *sii;  in sb_core_reset()  local
895 	sii = SI_INFO(sih);  in sb_core_reset()
896 	ASSERT(GOODREGS(sii->curmap));  in sb_core_reset()
897 	sb = REGS2SB(sii->curmap);  in sb_core_reset()
909 	W_SBREG(sii, &sb->sbtmstatelow,  in sb_core_reset()
912 	dummy = R_SBREG(sii, &sb->sbtmstatelow);  in sb_core_reset()
916 	if (R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_SERR) {  in sb_core_reset()
917 		W_SBREG(sii, &sb->sbtmstatehigh, 0);  in sb_core_reset()
919 	if ((dummy = R_SBREG(sii, &sb->sbimstate)) & (SBIM_IBE | SBIM_TO)) {  in sb_core_reset()
920 		AND_SBREG(sii, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));  in sb_core_reset()
924 	W_SBREG(sii, &sb->sbtmstatelow,  in sb_core_reset()
926 	dummy = R_SBREG(sii, &sb->sbtmstatelow);  in sb_core_reset()
931 	W_SBREG(sii, &sb->sbtmstatelow, ((bits | SICF_CLOCK_EN) << SBTML_SICF_SHIFT));  in sb_core_reset()
932 	dummy = R_SBREG(sii, &sb->sbtmstatelow);  in sb_core_reset()
964 	si_info_t *sii = SI_INFO(sih);  in sb_set_initiator_to()  local
975 		switch (BUSTYPE(sii->pub.bustype)) {  in sb_set_initiator_to()
977 			idx = sii->pub.buscoreidx;  in sb_set_initiator_to()
998 	INTR_OFF(sii, intr_val);  in sb_set_initiator_to()
1003 	tmp = R_SBREG(sii, &sb->sbimconfiglow);  in sb_set_initiator_to()
1005 	W_SBREG(sii, &sb->sbimconfiglow, (tmp & ~TO_MASK) | to);  in sb_set_initiator_to()
1009 	INTR_RESTORE(sii, intr_val);  in sb_set_initiator_to()
1068 	si_info_t *sii = SI_INFO(sih);  in sb_dumpregs()  local
1069 	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;  in sb_dumpregs()
1071 	origidx = sii->curidx;  in sb_dumpregs()
1073 	INTR_OFF(sii, intr_val);  in sb_dumpregs()
1075 	for (i = 0; i < sii->numcores; i++) {  in sb_dumpregs()
1080 		if (sii->pub.socirev > SONICS_2_2)  in sb_dumpregs()
1082 			          sb_corereg(sih, si_coreidx(&sii->pub), SBIMERRLOG, 0, 0),  in sb_dumpregs()
1083 			          sb_corereg(sih, si_coreidx(&sii->pub), SBIMERRLOGA, 0, 0));  in sb_dumpregs()
1087 		            R_SBREG(sii, &sb->sbtmstatelow), R_SBREG(sii, &sb->sbtmstatehigh),  in sb_dumpregs()
1088 		            R_SBREG(sii, &sb->sbidhigh), R_SBREG(sii, &sb->sbimstate),  in sb_dumpregs()
1089 		            R_SBREG(sii, &sb->sbimconfiglow), R_SBREG(sii, &sb->sbimconfighigh));  in sb_dumpregs()
1093 	INTR_RESTORE(sii, intr_val);  in sb_dumpregs()