Lines Matching full:sdio
2 * Broadcom SiliconBackplane SDIO/PCMCIA hardware-specific
94 uint32 funcintmask; /* SDIO Function Interrupt Mask, SDIO rev4 */
101 /* synchronized access to registers in SDIO clock domain */
118 uint32 cmd52rd; /* Cmd52RdCount, 0x110, rev8, SDIO: cmd52 reads */
119 uint32 cmd52wr; /* Cmd52WrCount, 0x114, rev8, SDIO: cmd52 writes */
120 uint32 cmd53rd; /* Cmd53RdCount, 0x118, rev8, SDIO: cmd53 reads */
121 uint32 cmd53wr; /* Cmd53WrCount, 0x11c, rev8, SDIO: cmd53 writes */
122 uint32 abort; /* AbortCount, 0x120, rev8, SDIO: aborts */
123 uint32 datacrcerror; /* DataCrcErrorCount, 0x124, rev8, SDIO: frames w/bad CRC */
124 uint32 rdoutofsync; /* RdOutOfSyncCount, 0x128, rev8, SDIO/PCMCIA: Rd Frm OOS */
125 uint32 wroutofsync; /* RdOutOfSyncCount, 0x12c, rev8, SDIO/PCMCIA: Wr Frm OOS */
126 uint32 writebusy; /* WriteBusyCount, 0x130, rev8, SDIO: dev asserted "busy" */
127 uint32 readwait; /* ReadWaitCount, 0x134, rev8, SDIO: read: no data avail */
128 uint32 readterm; /* ReadTermCount, 0x138, rev8, SDIO: rd frm terminates */
129 uint32 writeterm; /* WriteTermCount, 0x13c, rev8, SDIO: wr frm terminates */
144 uint32 chipid; /* SDIO ChipID Register, 0x330, rev31 */
145 uint32 eromptr; /* SDIO EromPtrOffset Register, 0x334, rev31 */
148 /* SDIO/PCMCIA CIS region */
179 #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation bit (rev 11) */
184 #define CS_PCMCIAMODE (1 << 0) /* Device Mode; 0=SDIO, 1=PCMCIA */
215 #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */