Lines Matching full:receive

38  *  basic DMA register set is per channel(transmit or receive)
156 /* receive channel control */
157 #define	RC_RE		((uint32)1 << 0)	/**< receive enable */
158 #define	RC_RO_MASK	0xfe			/**< receive frame offset */
160 #define	RC_FM		((uint32)1 << 8)	/**< direct fifo receive (pio) mode */
174 /* receive descriptor table pointer */
177 /* receive channel status */
179 #define	RS_RS_MASK	0xf000			/**< receive state */
185 #define	RS_RE_MASK	0xf0000			/**< receive errors */
201 #define	FA_SEL_RDD	0x40000			/**< receive dma data */
202 #define	FA_SEL_RDP	0x50000			/**< receive dma pointers */
205 #define	FA_SEL_RFD	0xc0000			/**< receive fifo data */
206 #define	FA_SEL_RFP	0xd0000			/**< receive fifo pointers */
207 #define	FA_SEL_RSD	0xe0000			/**< receive frame status data */
208 #define	FA_SEL_RSP	0xf0000			/**< receive frame status pointers */
334 /* receive channel control */
335 #define	D64_RC_RE		0x00000001	/**< receive enable */
336 #define	D64_RC_RO_MASK		0x000000fe	/**< receive frame offset */
338 #define	D64_RC_FM		0x00000100	/**< direct fifo receive (pio) mode */
357 #define	D64_RC_ROEXT_MASK	0x08000000	/**< receive frame offset extension bit */
376 #define DMA_CTRL_ROEXT		(1 << 11)	/* receive frame offset extension support */
379 /* receive descriptor table pointer */
382 /* receive channel status */
384 #define	D64_RS0_RS_MASK		0xf0000000     	/**< receive state */
393 #define	D64_RS1_RE_MASK		0xf0000000	/* receive errors */
408 #define	D64_FA_SEL_RDD		0x40000		/**< receive dma data */
409 #define	D64_FA_SEL_RDP		0x50000		/**< receive dma pointers */
412 #define	D64_FA_SEL_RFD		0xc0000		/**< receive fifo data */
413 #define	D64_FA_SEL_RFP		0xd0000		/**< receive fifo pointers */
414 #define	D64_FA_SEL_RSD		0xe0000		/**< receive frame status data */
415 #define	D64_FA_SEL_RSP		0xf0000		/**< receive frame status pointers */
445 /** receive frame status */